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Intel StrataFlash(R) Memory (J3)
256-Mbit (x8/x16)
Datasheet
Product Features
Performance -- 110/115/120/150 ns Initial Access Speed -- 125 ns Initial Access Speed (256 Mbit density only) -- 25 ns Asynchronous Page mode Reads -- 30 ns Asynchronous Page mode Reads (256Mbit density only) -- 32-Byte Write Buffer --6.8 s per byte effective programming time Software -- Program and Erase suspend support -- Flash Data Integrator (FDI), Common Flash Interface (CFI) Compatible Security -- 128-bit Protection Register --64-bit Unique Device Identifier --64-bit User Programmable OTP Cells -- Absolute Protection with VPEN = GND -- Individual Block Locking -- Block Erase/Program Lockout during Power Transitions
Architecture -- Multi-Level Cell Technology: High Density at Low Cost -- High-Density Symmetrical 128-Kbyte Blocks --256 Mbit (256 Blocks) (0.18m only) --128 Mbit (128 Blocks) --64 Mbit (64 Blocks) --32 Mbit (32 Blocks) Quality and Reliability -- Operating Temperature: -40 C to +85 C -- 100K Minimum Erase Cycles per Block -- 0.18 m ETOXTM VII Process (J3C) -- 0.25 m ETOXTM VI Process (J3A) Packaging and Voltage -- 56-Lead TSOP Package -- 64-Ball Intel(R) Easy BGA Package -- Lead-free packages available -- 48-Ball Intel(R) VF BGA Package (32 and 64 Mbit) (x16 only) -- VCC = 2.7 V to 3.6 V -- VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel's 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash(R) Memory (J3) device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bitper-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future devices. Using the same NOR-based ETOXTM technology as Intel's one-bit-per-cell products, the J3 device takes advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components are ideal for code and data applications where high density and low cost are required. Examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. By applying FlashFileTM memory family pinouts, J3 memory components allow easy design migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash(R) memory (28F640J5 and 28F320J5) devices. J3 memory components deliver a new generation of forward-compatible software support. By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density upgrades and optimized write capabilities of future Intel StrataFlash(R) memory devices. Manufactured on Intel(R) 0.18 micron ETOXTM VII (J3C) and 0.25 micron ETOXTM VI (J3A) process technology, the J3 memory device provides the highest levels of quality and reliability. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design.
Order Number: 290667-021 March 2005
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The 3 Volt Intel StrataFlash(R) Memory may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) 2005, Intel Corporation. All rights reserved. Intel and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others.
2
Datasheet
Contents
Contents
1.0 Introduction....................................................................................................................................7 1.1 1.2 2.0 2.1 2.2 3.0 3.1 3.2 3.3 4.0 4.1 4.2 4.3 4.4 5.0 5.1 5.2 6.0 6.1 6.2 7.0 7.1 7.2 7.3 7.4 7.5 7.6 8.0 8.1 8.2 8.3 9.0 9.1 Nomenclature .......................................................................................................................7 Conventions..........................................................................................................................7 Block Diagram ......................................................................................................................9 Memory Map .......................................................................................................................10 56-Lead TSOP Package .....................................................................................................11 Easy BGA (J3) Package .....................................................................................................12 VF-BGA (J3) Package ........................................................................................................13 Easy BGA Ballout (32/64/128/256 Mbit) .............................................................................14 56-Lead TSOP (32/64/128/256 Mbit)..................................................................................15 VF BGA Ballout (32 and 64 Mbit) .......................................................................................15 Signal Descriptions .............................................................................................................16 Absolute Maximum Ratings ................................................................................................18 Operating Conditions ..........................................................................................................18 DC Current Characteristics .................................................................................................19 DC Voltage Characteristics.................................................................................................20 Read Operations.................................................................................................................22 Write Operations .................................................................................................................26 Block Erase, Program, and Lock-Bit Configuration Performance .......................................27 Reset Operation..................................................................................................................29 AC Test Conditions.............................................................................................................29 Capacitance ........................................................................................................................30 Power-Up/Down Characteristics.........................................................................................31 Power Supply Decoupling...................................................................................................31 Reset Characteristics..........................................................................................................31 Bus Operations Overview ...................................................................................................32 9.1.1 Bus Read Operation ..............................................................................................33 9.1.2 Bus Write Operation ..............................................................................................33 9.1.3 Output Disable .......................................................................................................33 9.1.4 Standby..................................................................................................................34 9.1.5 Reset/Power-Down ................................................................................................34
Functional Overview .....................................................................................................................8
Package Information ...................................................................................................................11
Ballout and Signal Descriptions ................................................................................................14
Maximum Ratings and Operating Conditions...........................................................................18
Electrical Specifications .............................................................................................................19
AC Characteristics ......................................................................................................................22
Power and Reset Specifications ................................................................................................31
Bus Operations ............................................................................................................................32
Datasheet
3
Contents
9.2
Device Commands ............................................................................................................. 35
10.0 Read Operations.......................................................................................................................... 37 10.1 Read Array.......................................................................................................................... 37 10.1.1 Asynchronous Page Mode Read ........................................................................... 37 10.1.2 Enhanced Configuration Register (ECR)............................................................... 38 Read Identifier Codes ......................................................................................................... 39 10.2.1 Read Status Register............................................................................................. 39 Read Query/CFI.................................................................................................................. 41 Byte/Word Program ............................................................................................................ 42 Write to Buffer..................................................................................................................... 42 Program Suspend............................................................................................................... 43 Program Resume................................................................................................................ 43 Block Erase......................................................................................................................... 44 Block Erase Suspend ......................................................................................................... 44 Erase Resume .................................................................................................................... 45 Set Block Lock-Bit............................................................................................................... 46 Clear Block Lock-Bits.......................................................................................................... 46 Protection Register Program .............................................................................................. 47 13.3.1 Reading the Protection Register............................................................................ 47 13.3.2 Programming the Protection Register.................................................................... 47 13.3.3 Locking the Protection Register............................................................................. 47 Array Protection .................................................................................................................. 49 Set Read Configuration Register Command ...................................................................... 50 Status (STS) ....................................................................................................................... 50
10.2 10.3 11.1 11.2 11.3 11.4 12.1 12.2 12.3 13.1 13.2 13.3
11.0 Programming Operations ........................................................................................................... 42
12.0 Erase Operations......................................................................................................................... 44
13.0 Security Modes ............................................................................................................................ 46
13.4 14.1 14.2
14.0 Special Modes.............................................................................................................................. 50
Appendix A Common Flash Interface.................................................................................................52 Appendix B Flow Charts ......................................................................................................................59 Appendix C Design Considerations ...................................................................................................68 Appendix D Additional Information ....................................................................................................70 Appendix E Ordering Information.......................................................................................................71
4
Datasheet
Contents
Revision History
Date of Revision 07/07/99 08/03/99 09/07/99 Version -001 -002 -003 Original Version A0-A2 indicated on block diagram Changed Minimum Block Erase time,IOL, IOH, Page Mode and Byte Mode currents. Modified RP# on AC Waveform for Write Operations Changed Block Erase time and tAVWH Removed all references to 5 V I/O operation Corrected Ordering Information, Valid Combinations entries 12/16/99 -004 Changed Min program time to 211 s Added DU to Lead Descriptions table Changed Chip Scale Package to Ball Grid Array Package Changed default read mode to page mode Removed erase queuing from Figure 10, Block Erase Flowchart Added Program Max time Added Erase Max time Added Max page mode read current Moved tables to correspond with sections Fixed typographical errors in ordering information and DC parameter table Removed VCCQ1 setting and changed VCCQ2/3 to VCCQ1/2 03/16/00 -005 Added recommended resister value for STS pin Change operation temperature range Removed note that rp# could go to 14 V Removed VOL of 0.45 V; Removed VOH of 2.4 V Updated ICCR Typ values Added Max lock-bit program and lock times Added note on max measurements Updated cover sheet statement of 700 million units to one billion 06/26/00 -006 Corrected Table 10 to show correct maximum program times Corrected error in Max block program time in section 6.7 Corrected typical erase time in section 6.7 Updated cover page to reflect 100K minimum erase cycles Updated cover page to reflect 110 ns 32M read speed Removed Set Read Configuration command from Table 4 Updated Table 8 to reflect reserved bits are 1-7; not 2-7 Updated Table 16 bit 2 definition from R to PSS 2/15/01 -007 Changed VPENLK Max voltage from 0.8 V to 2.0 V, Section 6.4, DC Characteristics Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5, AC Characteristics-Read-Only Operations (1,2) Updated write parameter W13 (tWHRL) from 90 ns to 500 ns, Section 6.6, AC Characteristics-Write Operations Updated Max. Program Suspend Latency W16 (tWHRH1) from 30 to 75 s, Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance Description
(1,2,3)
04/13/01
-008
Revised Section 7.0, Ordering Information
Datasheet
5
Contents
Date of Revision
Version
Description Added Figure 4, 3 Volt Intel StrataFlash(R) Memory VF BGA Package (32 Mbit) Added Figure 5, 3 Volt Intel StrataFlash(R) Memory VF BGA Mechanical Specifications Updated Operating Temperature Range to Extended (Section 6.1 and Table 22)
07/27/01
-009
Reduced tEHQZ to 35 ns. Reduced tWHEH to 0 ns Added parameter values for -40 C operation to Lock-Bit and Suspend Latency Updated VLKO and VPENLK to 2.2 V Removed Note #4, Section 6.4 and Section 6.6 Minor text edits Added notes under lead descriptions for VF BGA Package Removed 3.0 V - 3.6 V Vcc, and Vccq columns under AC Characteristics
10/31/01
-010
Removed byte mode read current row un DC characteristics Added ordering information for VF BGA Package Minor text edits Changed datasheet to reflect the best known methods Updated max value for Clear Block Lock-Bits time Minor text edits Added nomenclature for J3C (0.18 m) devices. Added 115 ns access speed 64 Mb J3C device. Added 120 ns access speed 128 Mb J3C device. Added "TE" package designator for J3C TSOP package. Revised Asynchronous Page Read description. Revised Write-to-Buffer flow chart. Updated timing waveforms. Added 256-Mbit J3C pinout. Added 256Mbit device timings, device ID, and CFI information. Also corrected VLKO specification. Corrected memory block count from 257 to 255. Memory block count fix. Restructured the datasheet layout. Added lead-free part numbers and 8-word page information. Added Note to DC Voltage Characteristics table; "Speed Bin" to Read Operations table; Corrected format for AC Waveform for Reset Operation figure; Corrected "R" and "8W" headings in Enhanced Configuration Register table because they were transposed; Added 802 and 803 to ordering information and corrected 56Lead TSOP combination number. Corrected ordering information.
03/21/02
-011
12/12/02 01/24/03 12/09/03 1/3/04 1/23/04 1/23/04 5/19/04 7/7/04
-012 -013 -014 -015 -016 -016 -018 -019
11/23/04
-020
3/24/05
-021
6
Datasheet
256-Mbit J3 (x8/x16)
1.0
Introduction
This document describes the Intel StrataFlash(R) Memory (J3) device. It includes a description of device features, operations, and specifications.
1.1
Nomenclature
AMIN: AMAX: AMIN = A0 for x8 AMIN = A1 for x16 32 Mbit AMAX = A21 64 Mbit AMAX = A22 128 Mbit AMAX = A23 256 Mbit AMAX = A24 A group of flash cells that share common erase circuitry and erase simultaneously Indicates a logic zero (0) Command User Interface Multi-Level Cell One Time Programmable Protection Lock Register Protection Register Protection Register Data To write data to the flash array Reserved for Future Use Indicates a logic one (1) Status Register Status Register Data Refers to a signal or package connection name Refers to timing or voltage levels Write State Machine Extended Configuration Register eXtended Status Register
Block: Clear: CUI: MLC: OTP: PLR: PR: PRD Program: RFU: Set: SR: SRD: VPEN: VPEN: WSM: ECR: XSR:
1.2
Conventions
0x: 0b: k (noun): M (noun): Nibble Byte: Word: Kword: Kb: KB: Mb: MB: Brackets: Hexadecimal prefix Binary prefix 1,000 1,000,000 4 bits 8 bits 16 bits 1,024 words 1,024 bits 1,024 bytes 1,048,576 bits 1,048,576 bytes Square brackets ([]) will be used to designate group membership or to define a group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).
Datasheet
7
256-Mbit J3 (x8/x16)
2.0
Functional Overview
The Intel StrataFlash(R) memory family contains high-density memories organized as 32 Mbytes or 16Mwords (256-Mbit, available on the 0.18m lithography process only), 16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords (32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized as one-hundredtwenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is organized as sixtyfour 128-Kbyte erase blocks while the 32-Mbit device contains thirty-two 128-Kbyte erase blocks. A 128-bit Protection Register has multiple uses, including unique flash device identification. The device's optimized architecture and interface dramatically increases read performance by supporting page-mode reads. This read mode is ideal for non-clock memory systems. A Common Flash Interface (CFI) permits software algorithms to be used for entire families of devices. This allows device-independent, JEDEC ID-independent, and forward- and backwardcompatible software support for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work with all SCS-compliant flash memory devices, independent of system-level packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. A block erase operation erases one of the device's 128-Kbyte blocks typically within one second-- independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or program data from any other block. Similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming performance. By using the Write Buffer, data is programmed in buffer increments. This feature can improve system program performance more than 20 times over non-Write Buffer writes. Blocks are selectively and individually lockable in-system.Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block Lock-Bit and Clear Block Lock-Bits commands). The Status Register indicates when the WSM's block erase, program, or lock-bit configuration operation is finished. The STS (STATUS) output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status indication using STS minimizes both CPU overhead and system power consumption. When configured in level mode (default mode), it acts as a RY/ BY# signal. When low, STS indicates that the WSM is performing a block erase, program, or lockbit configuration. STS-high indicates that the WSM is ready for a new command, block erase is
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Datasheet
256-Mbit J3 (x8/x16)
suspended (and programming is inactive), program is suspended, or the device is in reset/powerdown mode. Additionally, the configuration command allows the STS signal to be configured to pulse on completion of programming and/or block erases. Three CE signals are used to enable and disable the device. A unique CE logic design (see Table 13, "Chip Enable Truth Table" on page 33) reduces decoder logic typically required for multi-chip designs. External logic is not required when designing a single chip, a dual chip, or a 4chip miniature card or SIMM module. The BYTE# signal allows either x8 or x16 read/writes to the device. BYTE#-low selects 8-bit mode; address A0 selects between the low byte and high byte. BYTE#-high enables 16-bit operation; address A1 becomes the lowest order address and address A0 is not used (don't care). A device block diagram is shown in Figure 4 on page 14. When the device is disabled (see Table 13 on page 33), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is at VIL, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from RP# going high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and the Status Register is cleared.
2.1
Block Diagram
Figure 1. 3 Volt Intel StrataFlash(R) Memory Block Diagram
D[15:0]
VCCQ
Output Buffer
Input Buffer
Query Output Latch/Multiplexer Write Buffer Identifier Register Status Register
I/O Logic Data Register CE Logic
VCC BYTE# CE0 CE1 CE2 WE# OE# RP#
Command User Interface
A[2:0]
Multiplexer Data Comparator
Y-Decoder A[MAX:MIN] Input Buffer
Y-Gating 32-Mbit: Thirty-two 64-Mbit: Sixty-four 128-Mbit: One-hundred twenty-eight 128-Kbyte Blocks Write State Machine Program/Erase Voltage Switch
STS VPEN
Address Latch Address Counter
X-Decoder
VCC GND
Datasheet
9
256-Mbit J3 (x8/x16)
2.2
Memory Map
Figure 2. Intel StrataFlash(R) Memory (J3) Memory Map
A[24-0]: 256 Mbit A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit
1FFFFFF
A[24-1]: 256 Mbit A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit
FFFFFF
128-Kbyte Block
1FE0000
255
64-Kword Block
FF0000
255
0FFFFFF 0FE0000
128-Kbyte Block
7FFFFF 127 7F0000
64-Kword Block
127
07FFFFF
3FFFFF
128-Kbyte Block
07E0000
63 3F0000
64-Kword Block
63
128-Kbyte Block
31 1F0000
64-Kword Block
31
03E0000
003FFFF
01FFFF
128-Kbyte Block
0020000 001FFFF 0000000
1 010000 00FFFF 0 000000
64-Kword Block 64-Kword Block
1 0
128-Kbyte Block
Byte-Wide (x8) Mode
Word Wide (x16) Mode
10
32-Mbit
64-Mbit
03FFFFF
1FFFFF
Datasheet
1 28-Mbit
256-Mbit
256-Mbit J3 (x8/x16)
3.0
3.1
Package Information
56-Lead TSOP Package
Figure 3. 56-Lead TSOP Package Drawing and Specifications
Z
See Notes 1 and 3
Pin 1
See Note 2
A2 e
E
See Detail B
Y
D1 D
A1 Seating Plane
See Detail A
A
Detail A Detail B
C
0
b
L
Table 1.
56-Lead TSOP Dimension Table
Millimeters Sym Min Nom Max 1.200 0.050 0.965 0.100 0.100 18.200 13.800 0.995 0.150 0.150 18.400 14.000 0.500 19.800 0.500 20.00 0.600 56 0 3 5 0.100 0.150 0.250 0.350 0.006 0.010 0 20.200 0.700 0.780 0.020 1.025 0.200 0.200 18.600 14.200 4 4 0.002 0.038 0.004 0.004 0.717 0.543 0.039 0.006 0.006 0.724 0.551 0.0197 0.787 0.024 56 3 5 0.004 0.014 0.795 0.028 0.040 0.008 0.008 0.732 0.559 4 4 Notes Min Inches Nom Max 0.047 Notes
Package Height Standoff Package Body Thickness Lead Width Lead Thickness Package Body Length Package Body Width Lead Pitch Terminal Dimension Lead Tip Length Lead Count Lead Tip Angle Seating Plane Coplanarity Lead to Package Offset
A A1 A2 b c D1 E e D L N
Y Z
Datasheet
11
256-Mbit J3 (x8/x16)
3.2
Easy BGA (J3) Package
Figure 4. Intel StrataFlash(R) Memory (J3) Easy BGA Mechanical Specifications
Ball A1 Corner Ball A1 Corner S1
D
1 A B C D E E F G H
2
3
4
5
6
7
8 A B C D E F G
8
7
6
5
4
3
2
1
S2
b
e H
Top View - Ball side down
Bottom View - Ball Side Up
A1 A2
A
Seating Plane
Y
Note: Drawing not to scale
Table 2.
Easy BGA Package Dimensions
Millimeters
Symbol Min Nom Max 1.200 0.250 0.780 0.330 9.900 12.900 14.900 0.430 10.000 13.000 15.000 1.000 64 0.100 1.400 2.900 3.900 1.500 3.000 4.000 1.600 3.100 4.100 1 1 1 0.0551 0.1142 0.1535 0.0591 0.1181 0.1575 0.530 10.100 13.100 15.100 1 1 1 0.0130 0.3898 0.5079 0.5866 0.0098 0.0307 0.0169 0.3937 0.5118 0.5906 0.0394 64 0.0039 0.0630 0.1220 0.1614 0.0209 0.3976 0.5157 0.5945 Notes Min
Inches
Nom Max 0.0472
Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width (32 Mb, 64 Mb, 128 Mb, 256 Mb) Package Body Length (32 Mb, 64 Mb, 128 Mb) Package Body Length (256 Mb) Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D (32/64/128/256 Mb) Corner to Ball A1 Distance Along E (32/64/128 Mb) Corner to Ball A1 Distance Along E (256 Mb)
A A1 A2 b D E E [e] N Y S1 S2 S2
NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information see www.intel.com/design/packtech/index.htm
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Datasheet
256-Mbit J3 (x8/x16)
3.3
VF-BGA (J3) Package
Figure 5. Intel StrataFlash(R) Memory (J3) VF BGA Mechanical Specifications
B a ll A 1 C o rn e r D S1 B all A1 C o rn e r
S2 1 A B C E D E F 2 3 4 5 6 7 8 A B C D E F b e 8 7 6 5 4 3 2 1
T o p V ie w - B u m p S id e D o w n
B o tt o m V ie w - B a ll S id e U p
A1 A2 A S e a t in g P la n e S id e V ie w N o te : D r a w in g n o t t o s ca le
Y
D im e n s io n s T a b le
M illim e te rs In ch es Sym b ol M in Nom M a x N o te s M in Pa c k a g e H e ig h t A 1.000 0 .1 5 0 0 .0 0 5 9 Ba ll H e ig h t A1 Pa c k a g e B o d y T h ic k n e s s A2 0 .6 6 5 Ba ll (L e a d ) W id th b 0 .3 2 5 0 .3 7 5 0.425 0 .0 1 2 8 D 7 .1 8 6 7 .2 8 6 7.386 1 0 .2 8 2 9 Pa c k a g e B o d y L e n g t h E 1 0 .7 5 0 10.850 1 0 .9 5 0 1 0 .4 2 3 2 Pitc h [e] 0 .7 5 0 Ba ll (L e a d ) C o u n t N 48 Se a tin g P la n e C o p la n a r ity Y 0.100 Co r n e r to B a ll A 1 D is ta n c e A lo n g D S1 0 .9 1 8 1 .0 1 8 1.118 1 0 .0 3 6 1 Co r n e r to B a ll A 1 D is ta n c e A lo n g E S2 3 .4 5 0 3 .5 5 0 3.650 1 0 .1 3 5 8 N o te : ( 1 ) P a c k a g e d im e n s io n s a re f o r r e f e re n c e o n ly . T h e s e d im e n s io n s a re e s t im a te s b a s e d o n d ie s iz e , a n d a r e su bj e c t t o c h a ng e . N om M ax 0 .0 3 9 4
0 .0 2 6 2 0 .0 1 4 8 0 .2 8 6 8 0 .4 2 7 2 0 .0 2 9 5 48 0 .0 4 0 1 0 .1 3 9 8
0 .0 1 6 7 0 .2 9 0 8 0 .4 3 1 1
0 .0 0 3 9 0 .0 4 4 0 0 .1 4 3 7
NOTES: 1. For Daisy Chain Evaluation Unit information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm 2. For Packaging Shipping Media information refer to the Intel Flash Memory Packaging Technology Web page at; www.intel.com/design/packtech/index.htm
Datasheet
13
256-Mbit J3 (x8/x16)
4.0
Ballout and Signal Descriptions
Intel StrataFlash(R) memory is available in three package types. Each density of the J3C is supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP) packages. A 48-ball VF BGA package is available on 32 and 64 Mbit devices. Figure 6, Figure 7, and Figure 8 show the pinouts.
4.1
Easy BGA Ballout (32/64/128/256 Mbit)
Figure 6. Intel StrataFlash(R) Memory Easy BGA Ballout (32/64/128/256 Mbit)
1 A A1 B A2 C A3 D A4 E D8 F BYTE# D0 G A23 128M H CE2# RFU VCC VSS D13 VSS Easy BGA Top View- Ball side down D7 A24 256M A24 D7 256M VSS D13 VSS VCC RFU CE2# Easy BGA Bottom View- Ball side up A0 D2 VCCQ D5 D6 D14 WE# WE# D14 D6 D5 VCCQ D2 A0 A23 128M H D10 D11 D12 RFU RFU OE# OE# RFU RFU D12 D11 D10 D0 BYTE# G D1 D9 D3 D4 RFU D15 STS STS D15 RFU D4 D3 D9 D1 D8 F A5 A11 RP# RFU RFU A16 A17 A17 A16 RFU RFU RP# A11 A5 A4 E A7 A10 A12 A15 RFU A20 A21 A21 A20 RFU A15 A12 A10 A7 A3 D VSS A9 CEO# A14 RFU A19 CE1# CE1# A19 RFU A14 CEO# A9 VSS A2 C A6 A8 VPEN A13 VCC A18 A22 A22 A18 VCC A13 VPEN A8 A6 A1 B 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 A
NOTES: 1. Address A22 is only valid on 64-Mbit densities and above, otherwise, it is a no connect (NC). 2. Address A23 is only valid on 128-Mbit densities and above, otherwise, it is a no connect (NC). 3. Address A24 is only valid on 256-Mbit densities and above, otherwise, it is a no connect (NC).
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Datasheet
256-Mbit J3 (x8/x16)
4.2
56-Lead TSOP (32/64/128/256 Mbit)
Figure 7. Intel StrataFlash(R) Memory 56-Lead TSOP (32/64/128/256 Mbit)
3 Volt Intel StrataFlash Memory 28F160S3 NC CE1 NC A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPP RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 28F320J5 NC CE1 A21 A20 A19 A18 A17 A16 VCC(4) A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 32/64/128M A22(1) CE1 A21 A20 A19 A18 A17 A16 VCC A15 A14 A13 A12 CE0 VPEN RP# A11 A10 A9 A8 GND A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 3 Volt Intel StrataFlash Memory 32/64/128M A24(3) WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# A23(2) CE2 28F320J5 NC WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCCQ GND DQ11 DQ3 DQ10 DQ2 VCC(4) DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC CE2 28F160S3 WP# WE# OE# STS DQ15 DQ7 DQ14 DQ6 GND DQ13 DQ5 DQ12 DQ4 VCC GND DQ11 DQ3 DQ10 DQ2 VCC DQ9 DQ1 DQ8 DQ0 A0 BYTE# NC NC
3 Volt Intel StrataFlash(R) Memory 56-Lead TSOP Standard Pinout 14 mm x 20 mm Top View
Highlights pinout changes
NOTES: 1. A22 exists on 64-, 128- and 256-Mbit densities. On 32-Mbit densities this signal is a no-connect (NC). 2. A23 exists on 128-Mbit densities. On 32- and 64-Mbit densities this signal is a no-connect (NC). 3. A24 exists on 256-Mbit densities. On 32-, 64- and 128-Mbit densities this signal is a no-connect (NC). 4. VCC = 5 V 10% for the 28F640J5/28F320J5.
4.3
VF BGA Ballout (32 and 64 Mbit)
Figure 8. Intel StrataFlash(R) Memory VF BGA Ballout (32 and 64 Mbit)
1 A A 14 B A5 1 C A 16 D A 17 E
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1 A
A 12
A 9
VE PN
VC C
A0 2
A 8
A 5
A 5
A 8
A0 2
VC C
VE PN
A 9
A2 1
A 14 B
A1 1
W# E
R# P
A9 1
A 18
A 6
A 3
A 3
A 6
A8 1
A 19
R# P
W# E
A 11
A 15 C
A3 1
A 10
A2 2
A1 2
A 7
A 4
A 2
A 2
A 4
A 7
A1 2
A 22
A0 1
A 13
A6 1 D
D 14
D 5
D1 1
D 2
D 8
C# E
A 1
A 1
C# E
D 8
D 2
D1 1
D 5
D 14
A7 1 E
VC CQ D 15 F VS S D 7
D 6
D2 1
D 3
D 9
D 0
VS S
VS S
D 0
D 9
D 3
D2 1
D 6
D 15
VC CQ F
D 13
D 4
VC C
D0 1
D 1
O# E
O# E
D 1
D0 1
VC C
D 4
D 13
D 7
VS S
V B A6 8 FG x T pV w- B ll S eD w o ie a id o n
V B A6x FG 8 B tto V w- B S eU o m ie all id p
NOTES: 1. CE# is equivalent to CE0, and CE1 and CE2 are internally grounded. 2. A22 exists on the 64 Mb density only. On the 32-Mbit density, this signal is a no-connect (NC). 3. STS not supported in this package. 4. x8 not supported in this package.
Datasheet
15
256-Mbit J3 (x8/x16)
4.4
Signal Descriptions
Table 3 describes active signals used.
Table 3.
Symbol A0
Signal Descriptions (Sheet 1 of 2)
Type Input Name and Function BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is turned off when BYTE# is high). ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are internally latched during a program cycle. 32-Mbit: A[21:0] 64-Mbit: A[22:0] 128-Mbit: A[23:0] 256-Mbit: A[24:0] LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data is internally latched during write operations. HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations. Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register reads. Data is internally latched during write operations in x16 mode. D[15-8] float in x8 mode CHIP ENABLES: Activates the device's control logic, input buffers, decoders, and sense amplifiers. When the device is de-selected (see Table 13 on page 33), power reduces to standby levels. All timing specifications are the same for these three signals. Device selection occurs with the first edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33). RESET/ POWER-DOWN: RP#-low resets internal automation and puts the device in powerdown mode. RP#-high enables normal operation. Exit from reset sets the device to read array mode. When driven low, RP# inhibits write operations which provides data protection during power transitions. OUTPUT ENABLE: Activates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low. Addresses and data are latched on the rising edge of WE#. STATUS: Indicates the status of the internal state machine. When configured in level mode (default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. For alternate configurations of the STATUS signal, see the Configurations command. STS is to be tied to VCCQ with a pull-up resistor. BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on D[7:0], while D[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#high places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowest-order address bit. ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or configuring lock-bits. With VPEN VPENLK, memory contents cannot be altered. CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited when VCC VLKO. Device operation at invalid Vcc voltages should not be attempted. I/O POWER SUPPLY: I/O Output-driver source voltage. This ball can be tied to VCC.
A[MAX:1]
Input
D[7:0]
Input/Output
D[15:8]
Input/Output
CE0, CE1, CE2
Input
RP#
Input
OE# WE#
Input Input
STS
Open Drain Output
BYTE#
Input
VPEN
Input
VCC VCCQ
Power Power
16
Datasheet
256-Mbit J3 (x8/x16)
Table 3.
Symbol GND NC RFU
Signal Descriptions (Sheet 2 of 2)
Type Supply -- -- Name and Function GROUND: Do not float any ground signals. NO CONNECT: Lead is not internally connected; it may be driven or floated. RESERVED for FUTURE USE: Balls designated as RFU are reserved by Intel for future device functionality and enhancement.
Datasheet
17
256-Mbit J3 (x8/x16)
5.0
5.1
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
This datasheet contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Absolute maximum ratings are shown in Table 4.
Warning:
Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Absolute Maximum Ratings
Parameter Temperature under Bias Extended Storage Temperature Voltage On Any signal Output Short Circuit Current Maximum Rating -40 C to +85 C -65 C to +125 C -2.0 V to +5.0 V(1) 100 mA(2)
Table 4.
NOTES: 1. All specified voltages are with respect to GND. Minimum DC voltage is -0.5 V on input/output signals and -0.2 V on VCC and VPEN signals. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output signals, VCC, and VPEN is VCC +0.5 V which, during transitions, may overshoot to VCC +2.0 V for periods <20 ns. 2. Output shorted for no more than one second. No more than one output shorted at a time.
5.2
Table 5.
Operating Conditions
Temperature and VCC Operating Conditions
Symbol TA VCC VCCQ Parameter Operating Temperature VCC1 Supply Voltage (2.7 V-3.6 V) VCCQ Supply Voltage (2.7 V-3.6 V) Min -40 2.70 2.70 Max +85 3.60 3.60 Unit C V V Test Condition Ambient Temperature -- --
18
Datasheet
256-Mbit J3 (x8/x16)
6.0
6.1
Table 6.
Electrical Specifications
DC Current Characteristics
DC Current Characteristics (Sheet 1 of 2)
VCCQ VCC 2.7 - 3.6V 2.7 - 3.6V Typ Max 1 10 Unit A A VCC = VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND VCC= VCC Max; VCCQ = VCCQ Max VIN = VCCQ or GND CMOS Inputs, VCC = VCC Max, Device is disabled (see Table 13, "Chip Enable Truth Table" on page 33), RP# = VCCQ 0.2 V TTL Inputs, VCC = VCC Max, Device is disabled (see Table 13), RP# = VIH RP# = GND 0.2 V, IOUT (STS) = 0 mA CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 13) f = 5 MHz, IOUT = 0 mA CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 4 word page mode reads. Device is enabled (see Table 13) f = 33 MHz, IOUT = 0 mA * CMOS Inputs, VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. * Device is enabled (see Table 13) f = 5 MHz, IOUT = 0 mA * CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. 30 54 mA * Device is enabled (see Table 13) f = 33 MHz, IOUT = 0 mA * Density: 128-, 64-, and 32- Mbit * CMOS Inputs,VCC = VCC Max, VCCQ = VCCQ Max using standard 8 word page mode reads. 26 46 mA * Device is enabled (see Table 13) f = 33 MHz, IOUT = 0 mA * Density: 256Mbit CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC 1,3 1 1 Test Conditions Notes
Symbol ILI ILO
Parameter Input and VPEN Load Current Output Leakage Current
50 ICCS VCC Standby Current 0.71 ICCD VCC Power-Down Current 50
120
A
1,2,3
2 120
mA A
15 4word Page 24
20
mA
29
mA
10 ICCR VCC Page Mode Read Current
15
mA
8word Page
ICCW
VCC Program or Set LockBit Current
35 40
60 70
mA mA
1,4
Datasheet
19
256-Mbit J3 (x8/x16)
Table 6.
DC Current Characteristics (Sheet 2 of 2)
VCCQ VCC 2.7 - 3.6V 2.7 - 3.6V Typ 35 40 Max 70 80 10 Unit mA mA mA CMOS Inputs, VPEN = VCC TTL Inputs, VPEN = VCC Device is enabled (see Table 13) 1,5 1,4 Test Conditions Notes
Symbol ICCE ICCWS ICCES
Parameter VCC Block Erase or Clear Block Lock-Bits Current VCC Program Suspend or Block Erase Suspend Current
NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact Intel's Application Support Hotline or your local sales office for information about typical specifications. 2. Includes STS. 3. CMOS inputs are either VCC 0.2 V or GND 0.2 V. TTL inputs are either VIL or VIH. 4. Sampled, not 100% tested. 5. ICCWS and ICCES are specified with the device selected. If the device is read or written while in erase suspend mode, the device's current draw is ICCR and ICCWS
6.2
Table 7.
DC Voltage Characteristics
DC Voltage Characteristics
Symbol VIL VIH Parameter Input Low Voltage Input High Voltage Min -0.5 2.0 Max 0.8 VCCQ + 0.5 0.4 VOL Output Low Voltage 0.2 0.85 x VCCQ VCCQ - 0.2 VPEN Lockout during Program, Erase and Lock-Bit Operations 2.2 V V V V Unit V V V VCCQ = VCCQ Min IOL = 2 mA VCCQ = VCCQ Min IOL = 100 A VCCQ = VCCQ Min IOH = -2.5 mA VCCQ = VCCQ Min IOH = -100 A 2,3,4,7 Test Conditions Notes 2, 6 2,6
1,2
VOH
Output High Voltage
1,2
VPENLK
20
Datasheet
256-Mbit J3 (x8/x16)
Table 7.
DC Voltage Characteristics
Symbol VPENH VLKO Parameter VPEN during Block Erase, Program, or Lock-Bit Operations VCC Lockout Voltage Min 2.7 2.0 Max 3.6 Unit V V Test Conditions Notes 3,4 5
NOTES: 1. Includes STS. 2. Sampled, not 100% tested. 3. Block erases, programming, and lock-bit configurations are inhibited when VPEN VPENLK, and not guaranteed in the range between VPENLK (max) and VPENH (min), and above VPENH (max). 4. Typically, VPEN is connected to VCC (2.7 V-3.6 V). 5. Block erases, programming, and lock-bit configurations are inhibited when VCC < VLKO, and not guaranteed in the range between VLKO (min) and VCC (min), and above VCC (max). 6. Includes all operational modes of the device including standby and power-up sequences. 7. VCC operating condition for standby has to meet typical operationg coditons.
Datasheet
21
256-Mbit J3 (x8/x16)
7.0
7.1
Table 8.
AC Characteristics
Read Operations
Read Operations (Sheet 1 of 2)
VCC = 2.7 V-3.6 V (3) VCCQ = 2.7 V-3.6 V (3) Notes Speed Bin -110 Min 110 115 120 120 125 110 115 120 120 125 110 115 120 120 125 50 32 Mbit 150 180 180 210 210 0 0 35 15 0 0 35 15 0 0 35 15 0 0 35 15 0 0 35 15 1,2,5 1,2,5 1,2,5 1,2,5 210 50 50 50 50 150 150 150 Max -115 Min Max Min -120 Max -125 Min Max -150 Min Max 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2,4 1,2 1,2 1,2
Asynchronous Specifications (All units in ns unless otherwise noted)
#
Sym
Parameter
Density 32 Mbit
R1
tAVAV
Read/Write Cycle Time
64 Mbit 128 Mbit 256 Mbit 32 Mbit
R2
tAVQV
Address to Output Delay
64 Mbit 128 Mbit 256 Mbit 32 Mbit
R3
tELQV
CEX to Output Delay
64 Mbit 128 Mbit 256 Mbit
R4
tGLQV
OE# to NonArray Output Delay
R5
tPHQV
RP# High to Output Delay
64 Mbit 128 Mbit 256 Mbit
R6 R7 R8 R9
tELQX tGLQX tEHQZ tGHQZ tOH tELFL/ tELFH
CEX to Output in Low Z OE# to Output in Low Z CEX High to Output in High Z OE# High to Output in High Z Output Hold from Address, CEX, or OE# Change, Whichever Occurs First CEX Low to BYTE# High or Low
R10
0
0
0
0
0
1,2,5
R11
10
10
10
10
10
1,2,5
22
Datasheet
256-Mbit J3 (x8/x16)
Table 8.
Read Operations (Sheet 2 of 2)
VCC = 2.7 V-3.6 V (3) VCCQ = 2.7 V-3.6 V (3) Notes Speed Bin -110 Min Max 1000 1000 0 25 25 0 25 25 -115 Min Max 1000 1000 0 25 25 Min -120 Max 1000 1000 0 30 25 -125 Min Max 1000 1000 0 25 25 -150 Min Max 1000 1000 1,2 1,2,5 1,2,5 5, 6 4
Asynchronous Specifications (All units in ns unless otherwise noted)
# R12 R13 R14 R15 R16
Sym tFLQV/ tFHQV tFLQZ tEHEL tAPA tGLQV
Parameter
Density
BYTE# to Output Delay BYTE# to Output in High Z CEx High to CEx Low Page Address Access Time OE# to Array Output Delay
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
1. See AC Input/Output Reference Waveforms for the maximum allowable input slew rate. 2. OE# may be delayed up to tELQV-tGLQV after the first edge of CE0, CE1, or CE2 that enables the device (see Table 13) without impact on tELQV. 3. See Figure 15, "Transient Input/Output Reference Waveform for VCCQ = 2.7 V-3.6 V" on page 29 and Figure 16, "Transient Equivalent Testing Load Circuit" on page 30 for testing characteristics. 4. When reading the flash array a faster tGLQV (R16) applies. Non-array reads refer to Status Register reads, query reads, or device identifier reads. 5. Sampled, not 100% tested. 6. For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Figure 9. Single Word Asynchronous Read Waveform
R1 R2 Address [A] R3 CEx [E] R9 OE# [G] WE# [W] R4 R16 R7 R6 Data [D/Q] R11 BYTE#[F] R5 RP# [P] R12 R13 R10 R8
Datasheet
23
256-Mbit J3 (x8/x16)
0606_16
NOTES: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13). 2. When reading the flash array a faster tGLQV (R16) applies. For non-array reads, R4 applies (i.e.: Status Register reads, query reads, or device identifier reads).
Figure 10. 4-Word Page Mode Read Waveform
R1 R2 A[MAX:3] [A] A[2:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R8 R10 R9 2 3 4 00 01 10 11
R6 R7 D[15:0] [Q] R5 RP# [P] 1
R10 R15
NOTE: CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
24
Datasheet
256-Mbit J3 (x8/x16)
Figure 11. 8-word Asynchronous Page Mode Read
R1 R2 A[MAX:4] [A] A[3:1] [A] R3 CEx [E] R4 OE# [G] WE# [W] R10 R8 R9 6 8
R6 R7 D[15:0] [Q] R5 RP# [P] BYTE# 1
R10 R15 2
NOTES: 1. CEX low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13). 2. In this diagram, BYTE# is asserted high.
Datasheet
25
256-Mbit J3 (x8/x16)
7.2
Table 9.
Write Operations
Write Operations
Versions Valid for All Speeds Parameter RP# High Recovery to WE# (CEX) Going Low CEX (WE#) Low to WE# (CEX) Going Low Write Pulse Width Data Setup to WE# (CEX) Going High Address Setup to WE# (CEX) Going High CEX (WE#) Hold from WE# (CEX) High Data Hold from WE# (CEX) High Address Hold from WE# (CEX) High Write Pulse Width High VPEN Setup to WE# (CEX) Going High Write Recovery before Read WE# (CEX) High to STS Going Low VPEN Hold from Valid SRD, STS Going High 0 Min 1 0 70 50 55 0 0 0 30 0 35 500 Max s ns ns ns ns ns ns ns ns ns ns ns ns 1,2,3 1,2,4 1,2,4 1,2,5 1,2,5 1,2, 1,2, 1,2, 1,2,6 1,2,3 1,2,7 1,2,8 1,2,3,8,9
Unit
Notes
# W1 W2 W3 W4 W5 W6 W7 W8 W9 W11 W12 W13 W15
Symbol tPHWL (tPHEL) tELWL (tWLEL) tWP tDVWH (tDVEH) tAVWH (tAVEH) tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL
NOTES:
CEX low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CEX high is defined at the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. Refer to AC Characteristics-Read-Only Operations. 2. A write operation can be initiated and terminated with either CEX or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. 5. Refer to Table 14 for valid AIN and DIN for block erase, program, or lock-bit configuration. 6. Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL. 7. For array access, tAVQV is required in addition to tWHGL for any accesses after a write. 8. STS timings are based on STS configured in its RY/BY# default mode. 9. VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[1,3,4:5] = 0).
26
Datasheet
256-Mbit J3 (x8/x16)
7.3
Block Erase, Program, and Lock-Bit Configuration Performance
Table 10. Configuration Performance
# W16 W16 tWHQV3 tEHQV3 Sym Parameter Write Buffer Byte Program Time (Time to Program 32 bytes/16 words) Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write to Buffer Command) W16 W16 W16 W16 W16 tWHQV4 tEHQV4 tWHQV5 tEHQV5 tWHQV6 tEHQV6 tWHRH1 tEHRH1 tWHRH tEHRH Block Erase Time Set Lock-Bit Time Clear Block Lock-Bits Time Program Suspend Latency Time to Read Erase Suspend Latency Time to Read Typ 218 210 0.8 1.0 64 0.5 25 26 Max(8) 654 630 2.4 5.0 75/85 0.70/1.4 75/90 35/40 Unit s s sec sec s sec s s Notes 1,2,3,4,5,6,7 1,2,3,4 1,2,3,4 1,2,3,4 1,2,3,4,9 1,2,3,4,10 1,2,3,9 1,2,3,9
NOTES: 1. Typical values measured at TA = +25 C and nominal voltages. Assumes corresponding lock-bits are not set. Subject to change based on device characterization. 2. These performance numbers are valid for all speed versions. 3. Sampled but not 100% tested. 4. Excludes system-level overhead. 5. These values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. Effective per-byte program time (tWHQV1, tEHQV1) is 6.8 s/byte (typical). 7. Effective per-word program time (tWHQV2, tEHQV2) is 13.6 s/word (typical). 8. Max values are measured at worst case temperature and VCC corner after 100k cycles (except as noted). 9. Max values are expressed at -25 C/-40 C. 10.Max values are expressed at 25 C/-40 C.
Datasheet
27
256-Mbit J3 (x8/x16)
Figure 12. Asynchronous Write Waveform
W5 ADDRESS [A] W6 CEx (WE#) [E (W)] W2 WE# (CEx) [W (E)] OE# [G] W4 DATA [D/Q] D W13 STS[R] W1 RP# [P] W11 VPEN [V] W7 W3 W9 W8
Figure 13. Asynchronous Write to Read Waveform
W5 Address [A] W6 CE# [E] W2 WE# [W] W12 OE# [G] W4 Data [D/Q] W1 RST#/ RP# [P] W11 VPEN [V] D W7 W3 W8
28
Datasheet
256-Mbit J3 (x8/x16)
7.4
Reset Operation
Figure 14. AC Waveform for Reset Operation
VIH VIL
P2
STS (R)
RP# (P)
VIH VIL
P1
NOTE: STS is shown in its default mode (RY/BY#).
Table 11. Reset Specifications
# P1 Sym tPLPH tPHRH Parameter RP# Pulse Low Time (If RP# is tied to VCC, this specification is not applicable) RP# High to Reset during Block Erase, Program, or Lock-Bit Configuration Min 35 Max Unit s Notes 1,2
P2
100
ns
1,3
NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required RP# Pulse Low Time is 100 ns. 3. A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
7.5
AC Test Conditions
Figure 15. Transient Input/Output Reference Waveform for VCCQ = 2.7 V-3.6 V
VCCQ Input VCCQ/2 0.0
NOTE: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Test Points
VCCQ/2
Output
Datasheet
29
256-Mbit J3 (x8/x16)
Figure 16. Transient Equivalent Testing Load Circuit
1.3V 1N914 RL = 3.3 k Device Under Test Out CL
NOTE: CL Includes Jig Capacitance. Test Configuration VCCQ = VCC = 2.7 V-3.6 V CL (pF) 30
7.6
Capacitance
TA = +25 C, f = 1 MHz
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Type 6 8 Max 8 12 Unit pF pF Condition VIN = 0.0 V VOUT = 0.0 V
NOTES: 1. Sampled, not 100% tested.
30
Datasheet
256-Mbit J3 (x8/x16)
8.0
Power and Reset Specifications
This section provides an overview of system level considerations for the Intel StrataFlash(R) memory family device. This section provides a brief description of power-up, power-down, decoupling and reset design considerations.
8.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is recommended to power-up and power-down VCC and VCCQ together. It is also recommended to power-up VPEN with or slightly after VCC. Conversely, VPEN must power down with or slightly before VCC.
8.2
Power Supply Decoupling
When the device is enabled, many internal conditions change. Circuits are energized, charge pumps are switched on, and internal voltage nodes are ramped. All of this internal activities produce transient signals. The magnitude of the transient signals depends on the device and system loading. To minimize the effect of these transient signals, a 0.1 F ceramic capacitor is required across each VCC/VSS and VCCQ signal. Capacitors should be placed as close as possible to device connections. Additionally, for every eight flash devices, a 4.7 F electrolytic capacitor should be placed between VCC and VSS at the power supply connection. This 4.7 F capacitor should help overcome voltage slumps caused by PCB (printed circuit board) trace inductance.
8.3
Reset Characteristics
By holding the flash device in reset during power-up and power-down transitions, invalid bus conditions may be masked. The flash device enters reset mode when RP# is driven low. In reset, internal flash circuitry is disabled and outputs are placed in a high-impedance state. After return from reset, a certain amount of time is required before the flash device is able to perform normal operations. After return from reset, the flash device defaults to asynchronous page mode. If RP# is driven low during a program or erase operation, the program or erase operation will be aborted and the memory contents at the aborted block or address are no longer valid. See Figure 14, "AC Waveform for Reset Operation" on page 29 for detailed information regarding reset timings.
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256-Mbit J3 (x8/x16)
9.0
Bus Operations
This section provides an overview of device bus operations. The on-chip Write State Machine (WSM) manages all erase and program algorithms. The system CPU provides control of all insystem read, write, and erase operations of the device via the system bus. Device commands are written to the CUI to control all of the flash memory device's operations. The CUI does not occupy an addressable memory location; it's the mechanism through which the flash device is controlled.
9.1
Bus Operations Overview
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Table 12. Bus Operations
Mode Read Array Output Disable Standby Reset/Power-Down Mode Read Identifier Codes RP# VIH VIH VIH VIL VIH VIH VIH VIH VIH CE[2:0](1) Enabled Enabled Disabled X Enabled OE#(2) VIL VIH X X VIL VIL VIL VIL VIH WE#(2) VIH VIH X X VIH VIH VIH VIH VIL Address X X X X See Table 17 See Table 10.3 X X X VPEN X X X X X Data(3) DOUT High Z High Z High Z Note 8 STS (default mode) High Z(7) X X High Z(7) High Z(7) High Z(7) Notes 4,5,6
Read Query Read Status (WSM off) Read Status (WSM on) Write
Enabled Enabled Enabled Enabled
X X X VPENH
Note 9 DOUT D7 = DOUT D[15:8] = High Z D[6:0] = High Z DIN
X
6,10,11
NOTES: 1. See Table 13 on page 33 for valid CE configurations. 2. OE# and WE# should never be enabled simultaneously. 3. D refers to D[7:0] if BYTE# is low and D[15:0] if BYTE# is high. 4. Refer to DC Characteristics. When VPEN VPENLK, memory contents can be read, but not altered. 5. X can be VIL or VIH for control and address signals, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and VPENH voltages. 6. In default mode, STS is VOL when the WSM is executing internal block erase, program, or lock-bit configuration algorithms. It is VOH when the WSM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode. 7. High Z will be VOH with an external pull-up resistor. 8. See Section 10.2, "Read Identifier Codes" on page 39 for read identifier code data. 9. See Section 10.3, "Read Query/CFI" on page 41 for read query data. 10.Command writes involving block erase, program, or lock-bit configuration are reliably executed when VPEN = VPENH and VCC is within specification.
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256-Mbit J3 (x8/x16)
Table 13. Chip Enable Truth Table
CE2 VIL VIL VIL VIL VIH VIH VIH VIH CE1 VIL VIL VIH VIH VIL VIL VIH VIH CE0 VIL VIH VIL VIH VIL VIH VIL VIH DEVICE Enabled Disabled Disabled Disabled Enabled Enabled Enabled Disabled
NOTE: For single-chip applications, CE2 and CE1 can be connected to VIL.
9.1.1
Bus Read Operation
To perform a bus read operation, CEx (refer to Table 13 on page 33) and OE# must be asserted. CEx is the device-select control; when active, it enables the flash memory device. OE# is the dataoutput control; when active, the addressed flash memory data is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See Section 7.1, "Read Operations" on page 22. Refer to Section 10.0, "Read Operations" on page 37 for details on reading from the flash array, and refer to Section 14.0, "Special Modes" on page 50 for details regarding all other available read states.
9.1.2
Bus Write Operation
Writing commands to the Command User Interface enables various modes of operation, including the reading of array data, CFI data, identifier codes, inspection and clearing of the Status Register, and, when VPEN = VPENH, block erasure, program, and lock-bit configuration. The Block Erase command requires appropriate command data and an address within the block to be erased. The Byte/Word Program command requires the command and address of the location to be written. Set Block Lock-Bit commands require the command and block within the device to be locked. The Clear Block Lock-Bits command requires the command and address within the device. The CUI does not occupy an addressable memory location. It is written when the device is enabled and WE# is active. The address and data needed to execute a command are latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables the device (see Table 13 on page 33). Standard microprocessor write timings are used.
9.1.3
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled. Output signals D[15:0] are placed in a high-impedance state.
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256-Mbit J3 (x8/x16)
9.1.4
Standby
CE0, CE1, and CE2 can disable the device (see Table 13 on page 33) and place it in standby mode. This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are placed in a high-impedance state independent of OE#. If deselected during block erase, program, or lock-bit configuration, the WSM continues functioning, and consuming active power until the operation completes.
9.1.5
Reset/Power-Down
RP# at VIL initiates the reset/power-down mode. In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. RP# must be held low for a minimum of tPLPH. Time tPHQV is required after return from reset mode until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to read array mode and Status Register is set to 0x80. During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In default mode, STS transitions low and remains low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert RP# during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. If a CPU reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. Intel StrataFlash(R) memory family devices allow proper initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU.
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256-Mbit J3 (x8/x16)
9.2
Device Commands
When the VPEN voltage VPENLK, only read operations from the Status Register, CFI, identifier codes, or blocks are enabled. Placing VPENH on VPEN additionally enables block erase, program, and lock-bit configuration operations. Device operations are selected by writing specific commands into the CUI. Table 14, "Command Bus-Cycle Definitions" on page 35 defines these commands.
Table 14. Command Bus-Cycle Definitions (Sheet 1 of 2)
Command Scalable or Basic Command Set(2) SCS/BCS SCS/BCS SCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS/BCS SCS SCS Bus Cycles Req'd. 1 2 2 2 1 >2 2 2 1 1 2 2 First Bus Cycle Oper(3) Write Write Write Write Write Write Write Write Write Write Write Write Addr(4) X X X X X BA X BA X X X X Data(5,6) 0xFF 0X90 0x98 0x70 0x50 0xE8 0x40 or 0x10 0x20 0xB0 0xD0 0xB8 0x60 Write Write X BA CC 0x01 Write Write Write BA PA BA N PD 0xD0 Read Read Read IA QA X ID QD SRD Second Bus Cycle Notes Oper(3) Addr(4) Data(5,6) 1 1,7 1 1,8 1 1,9, 10, 11 1,12,13 1,11,12 1,12,14 1,12 1 1
Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write to Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Set Block Lock-Bit
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256-Mbit J3 (x8/x16)
Table 14. Command Bus-Cycle Definitions (Sheet 2 of 2)
Command Scalable or Basic Command Set(2) SCS Bus Cycles Req'd. 2 2 First Bus Cycle Oper(3) Write Write Addr(4) X X Data(5,6) 0x60 0xC0 Second Bus Cycle Notes Oper(3) Write Write Addr(4) X PA Data(5,6) 0xD0 PD 1,15 1
Clear Block Lock-Bits Protection Program
NOTES: 1. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 2. The Basic Command Set (BCS) is the same as the 28F008SA Command Set or Intel Standard Command Set. The Scalable Command Set (SCS) is also referred to as the Intel Extended Command Set. 3. Bus operations are defined in Table 12. 4. X = Any valid address within the device. BA = Address within the block. IA = Identifier Code Address: see Table 17. QA = Query database Address. PA = Address of memory location to be programmed. RCD = Data to be written to the read configuration register. This data is presented to the device on A[16:1]; all other address inputs are ignored. 5. ID = Data read from Identifier Codes. QD = Data read from Query database. SRD = Data read from Status Register. See Table 18 for a description of the Status Register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. CC = Configuration Code. 6. The upper byte of the data bus (D[15:8]) during command writes is a "Don't Care" in x16 operation. 7. Following the Read Identifier Codes command, read operations access manufacturer, device and block lock codes. See Section 10.2 for read identifier code data. 8. If the WSM is running, only D7 is valid; D[15:8] and D[6:0] float, which places them in a high-impedance state. 9. After the Write to Buffer command is issued check the XSR to make sure a buffer is available for writing. 10.The number of bytes/words to be written to the Write Buffer = N + 1, where N = byte/word count argument. Count ranges on this device for byte mode are N = 00H to N = 1FH and for word mode are N = 0x00 to N = 0x0F. The third and consecutive bus cycles, as determined by N, are for writing data into the Write Buffer. The Confirm command (0xD0) is expected after exactly N + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. See Figure 18, "Write to Buffer Flowchart" on page 59 for additional information 11.The write to buffer or erase operation does not begin until a Confirm command (0xD0) is issued. 12.Attempts to issue a block erase or program to a locked block. 13.Either 0x40 or 0x10 are recognized by the WSM as the byte/word program setup. 14.Program suspends can be issued after either the Write-to-Buffer or Word/Byte-Program operation is initiated. 15.The clear block lock-bits operation simultaneously clears all block lock-bits.
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Datasheet
256-Mbit J3 (x8/x16)
10.0
Read Operations
The device supports four types of read modes: Read Array, Read Identifier, Read Status, and CFI query. Upon power-up or return from reset, the device defaults to read array mode. To change the device's read mode, the appropriate read-mode command must be written to the device. (See Section 9.2, "Device Commands" on page 35.) See Section 14.0, "Special Modes" on page 50 for details regarding read status, read ID, and CFI query modes. Upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. Otherwise, write the appropriate read mode command (Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI. Six control signals dictate the data flow in and out of the component: CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled (see Table 13, "Chip Enable Truth Table" on page 33), and OE# must be driven active to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled (see Table 13), select the memory device. OE# is the data output (D[15:0]) control and, when active, drives the selected memory data onto the I/O bus. WE# must be at VIH.
10.1
Read Array
Upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. The device defaults to four-word asynchronous read page mode. The Read Array command also causes the device to enter read array mode. The device remains enabled for reads until another command is written. If the internal WSM has started a block erase, program, or lockbit configuration, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase or Program Suspend command. The Read Array command functions independently of the VPEN voltage.
10.1.1
Asynchronous Page Mode Read
There are two Asynchronous Page mode configurations that are available depending on the user's system design requirements:
* Four-Word Page mode: This is the default mode on power-up or reset. Array data can be
sensed up to four words (8 Bytes) at a time.
* Eight-Word Page mode: Array data can be sensed up to eight words (16 Bytes) at a time. This
mode must be enabled on power-up or reset by using the command sequence found in Table 14, "Command Bus-Cycle Definitions" on page 35. Address bits A[3:1] determine which word is output during a read operation, and A[3:0] determine which byte is output for a x8 bus width. After the initial access delay, the first word out of the page buffer corresponds to the initial address. In Four-Word Page mode, address bits A[2:1] determine which word is output from the page buffer for a x16 bus width, and A[2:0] determine which byte is output from the page buffer for a x8 bus width. Subsequent reads from the device come from the page buffer. These reads are output on D[15:0] for a x16 bus width and D[7:0] for a x8 bus width after a minimum delay as long as A[2:0] (Four-Word Page mode) or A[3:0] (Eight-Word Page mode) are the only address bits that change. Data can be read from the page buffer multiple times, and in any order. In Four-Word Page Mode, if address bits A[MAX:3] (A[MAX:4] for Eight-Word Page Mode) change at any time, or if CE# is toggled, the device will sense and load new data into the page buffer. Asynchronous Page Mode is the default read mode on power-up or reset.
Datasheet
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256-Mbit J3 (x8/x16)
To perform a page mode read after any other operation, the Read Array command must be issued to read from the flash array. Asynchronous page mode reads are permitted in all blocks and are used to access register information. During register access, only one word is loaded into the page buffer.
10.1.2
Enhanced Configuration Register (ECR)
The Enhanced Configuration Register (ECR) is a volatile storage register that when addressed to by the Set Enhanced Configuration Register command, and can select between Four-Word Page mode and Eight-Word Page mode. The ECR is volatile; all bits will be reset to default values when RP# is deasserted or power is removed from the device. To modify ECR settings, use the Set Enhanced Configuration Register command. The Set Enhanced Configuration Register command is written along with the configuration register value, which is placed on the lower 16 bits of the address bus A[15:0]. This is followed by a second write that confirms the operation and again presents the enhanced configuration register data on the address bus. After executing this command, the device returns to Read Array mode. The ECR is shown in Table 15, "Enhanced Configuration Register" on page 38.
Note:
For forward compatibility reasons, if the 8-word Asynchronous Page mode is to be used on J3C, a Clear Status Register command must be issued after issuing the Set Enhanced Configuration Register command. See Table 16, "J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition" on page 38 for further details.
Table 15. Enhanced Configuration Register
Res. R ECR .15 R ECR .14 8W ECR .13 R ECR .12 R ECR .11 R ECR .10 R ECR .9 R ECR .8 Reserved R ECR .7 R ECR .6 R ECR .5 R ECR .4 R ECR .3 R ECR .2 R ECR .1 R ECR .0
BITS ECR[15:14] ECR[13] ECR[12:0] Reserved
DESCRIPTION
NOTES Reserved for Future Use. Set to 0 until further notice.
* "1" = 8Word Page mode * "0" = 4Word Page mode Reserved NOTE: Any reserved bits should be set to 0. Reserved for Future Use. Set to 0 until further notice.
Table 16. J3C Asynchronous 8-Word Page Mode Command Bus-Cycle Definition
Command Set Enhanced Configuration Register (Set ECR) Bus Cycles Req'd. 3 First Bus Cycle Oper Write Addr(1) ECD Data 0x60 Second Bus Cycle Oper Write Addr(1) ECD Data 0x04 Third Bus Cycle Oper Write Addr(1) X Data 0x50
NOTE: X = Any valid address within the device. ECD = Enhanced Configuration Register Data.
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256-Mbit J3 (x8/x16)
10.2
Read Identifier Codes
The Read identifier codes operation outputs the manufacturer code, device-code, and the block lock configuration codes for each block (See Section 9.2, "Device Commands" on page 35 for details on issuing the Read Device Identifier command). Page-mode reads are not supported in this read mode. To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPEN voltage. This command is valid only when the WSM is off or the device is suspended. Following the Read Identifier Codes command, the following information can be read.
Table 17. Read Identifier Codes
Code Manufacture Code Device Code 32-Mbit 64-Mbit 128-Mbit 256-Mbit Block Lock Configuration * Block Is Unlocked * Block Is Locked * Reserved for Future Use Address(1) 00000 00001 00001 00001 00001
X0002(2)
Data (00) 89 (00) 16 (00) 17 (00) 18 (00) 1D
D0 = 0 D0 = 1 D[7:1]
NOTES: 1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest order address line is A1. Data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. X selects the specific block's lock configuration code. 3. D[7:1] are invalid and should be ignored.
10.2.1
Read Status Register
The Status Register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. It may be read only after the specified time W12 (see Table 9, "Write Operations" on page 26). After writing this command, all subsequent read operations output data from the Status Register until another valid command is written. Page-mode reads are not supported in this read mode. The Status Register contents are latched on the falling edge of OE# or the first edge of CE0, CE1, or CE2 that enables the device (see Table 13, "Chip Enable Truth Table" on page 33). OE# must toggle to VIH or the device must be disabled before further reads to update the Status Register latch. The Read Status Register command functions independently of the VPEN voltage. During a program, block erase, set lock-bit, or clear lock-bit command sequence, only SR.7 is valid until the Write State Machine completes or suspends the operation. Device I/O signals D[6:0] and D[15:8] are placed in a high-impedance state. When the operation completes or suspends (check SR.7), all contents of the Status Register are valid when read.
Datasheet
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256-Mbit J3 (x8/x16)
Table 18. Status Register Definitions
WSMS bit 7 High Z When Busy? No Yes ESS bit 6 ECLBS bit 5 PSLBS bit 4 VPENS bit 3 PSS bit2 DPS bit 1 R bit 0
Status Register Bits SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR LOCK-BITSSTATUS 1 = Error in Block Erasure or Clear Lock-Bits 0 = Successful Block Erase or Clear Lock-Bits SR.4 = PROGRAM AND SET LOCK-BIT STATUS 1 = Program Error / Error in Setting Lock-Bit 0 = Successful Program/Set Block Lock Bit SR.3 = PROGRAMMING VOLTAGE STATUS 1 = Low Programming Voltage Detected, Operation Aborted 0 = Programming Voltage OK SR.2 = PROGRAM SUSPEND STATUS 1 = Program suspended 0 = Program in progress/completed SR.1 = DEVICE PROTECT STATUS 1 = Block Lock-Bit Detected, Operation Abort 0 = Unlock
Notes Check STS or SR.7 to determine block erase, program, or lock-bit configuration completion. SR[6:0] are not driven while SR.7 = "0."
Yes Yes Yes
If both SR.5 and SR.4 are "1"s after a block erase or lock-bit configuration attempt, an improper command sequence was entered.
Yes
SR.3 does not provide a continuous programming voltage level indication. The WSM interrogates and indicates the programming voltage level only after Block Erase, Program, Set Block Lock-Bit, or Clear Block Lock-Bits command sequences.
Yes
SR.1 does not provide a continuous indication of block lock-bit values. The WSM interrogates the block lock-bits only after Block Erase, Program, or Lock-Bit configuration command sequences. It informs the system, depending on the attempted operation, if the block lock-bit is set. Read the block lock configuration codes using the Read Identifier Codes command to determine block lock-bit status. SR0 is reserved for future use and should be masked when polling the Status Register.
Yes
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
Table 19. Extended Status Register Definitions
WBS bit 7 High Z When Busy? No Yes Reserved Bits 6 -- 0
Status Register Bits
Notes After a Buffer-Write command, XSR.7 = 1 indicates that a Write Buffer is available. SR[6:0] are reserved for future use and should be masked when polling the Status Register.
XSR.7 = WRITE BUFFER STATUS 1 = Write buffer available 0 = Write buffer not available XSR.6-XSR0 = RESERVED FOR FUTURE ENHANCEMENTS
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Datasheet
256-Mbit J3 (x8/x16)
10.3
Read Query/CFI
The query register contains an assortment of flash product information such as block size, density, allowable command sets, electrical specifications and other product information. The data contained in this register conforms to the Common Flash Interface (CFI) protocol. To obtain any information from the query register, execute the Read Query Register command. See Section 9.2, "Device Commands" on page 35 for details on issuing the CFI Query command. Refer to Appendix A, "Query Structure Overview" on page 53 for a detailed explanation of the CFI register. Information contained in this register can only be accessed by executing a single-word read.
Datasheet
41
256-Mbit J3 (x8/x16)
11.0
Programming Operations
The device supports two different programming methods: word programming, and write-buffer programming. Successful programming requires the addressed block to be unlocked. An attempt to program a locked block will result in the operation aborting, and SR.1 and SR.4 being set, indicating a programming error. The following sections describe device programming in detail.
11.1
Byte/Word Program
Byte/Word program is executed by a two-cycle command sequence. Byte/Word program setup (standard 0x40 or alternate 0x10) is written followed by a second write that specifies the address and data (latched on the rising edge of WE#). The WSM then takes over, controlling the program and program verify algorithms internally. After the program sequence is written, the device automatically outputs SRD when read (see Figure 20, "Byte/Word Program Flowchart" on page 61). The CPU can detect the completion of the program event by analyzing the STS signal or SR.7. When program is complete, SR.4 should be checked. If a program error is detected, the Status Register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The CUI remains in Read Status Register mode until it receives another command. Reliable byte/word programming can only occur when VCC and VPEN are valid. If a byte/word program is attempted while VPEN VPENLK, SR.4 and SR.3 will be set. Successful byte/word programs require that the corresponding block lock-bit be cleared. If a byte/word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.
11.2
Write to Buffer
To program the flash device, a Write to Buffer command sequence is initiated. A variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. First, the Write to Buffer Setup command is issued along with the Block Address (see Figure 18, "Write to Buffer Flowchart" on page 59). At this point, the eXtended Status Register (XSR, see Table 19) information is loaded and XSR.7 reverts to "buffer available" status. If XSR.7 = 0, the write buffer is not available. To retry, continue monitoring XSR.7 by issuing the Write to Buffer setup command with the Block Address until XSR.7 = 1. When XSR.7 transitions to a "1," the buffer is ready for loading. Next, a word/byte count is given to the part with the Block Address. On the next write, a device start address is given along with the write buffer data. Subsequent writes provide additional device addresses and data, depending on the count. All subsequent addresses must lie within the start address plus the count. Internally, this device programs many flash cells in parallel. Because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., A[4:0] of the start address = 0).
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Datasheet
256-Mbit J3 (x8/x16)
After the final buffer data is given, a Write Confirm command is issued. This initiates the WSM (Write State Machine) to begin copying the buffer data to the flash array. If a command other than Write Confirm is written to the device, an "Invalid Command/Sequence" error will be generated and SR.5 and SR.4 will be set. For additional buffer writes, issue another Write to Buffer Setup command and check XSR.7. If an error occurs while writing, the device will stop writing, and SR.4 will be set to indicate a program failure. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. If a program error is detected, the Status Register should be cleared. Any time SR.4 and/or SR.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more Write to Buffer commands. Additionally, if the user attempts to program past an erase block boundary with a Write to Buffer command, the device will abort the write to buffer operation. This will generate an "Invalid Command/Sequence" error and SR.5 and SR.4 will be set. Reliable buffered writes can only occur when VPEN = VPENH. If a buffered write is attempted while VPEN VPENLK, SR.4 and SR.3 will be set. Buffered write attempts with invalid VCC and VPEN voltages produce spurious results and should not be attempted. Finally, successful programming requires that the corresponding block lock-bit be reset. If a buffered write is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.
11.3
Program Suspend
The Program Suspend command allows program interruption to read data in other flash memory locations. Once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the Program Suspend command requests that the WSM suspend the program sequence at a predetermined point in the algorithm. The device continues to output SRD when read after the Program Suspend command is written. Polling SR.7 can determine when the programming operation has been suspended. When SR.7 = 1, SR.2 should also be set, indicating that the device is in the program suspend mode. STS in level RY/BY# mode will also transition to VOH. Specification tWHRH1 defines the program suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while programming is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Program Resume. After a Program Resume command is written, the WSM will continue the programming process. SR.2 and SR.7 will automatically clear and STS in RY/BY# mode will return to VOL. After the Program Resume command is written, the device automatically outputs SRD when read. VPEN must remain at VPENH and VCC must remain at valid VCC levels (the same VPEN and VCC levels used for programming) while in program suspend mode. Refer to Figure 21, "Program Suspend/Resume Flowchart" on page 62.
11.4
Program Resume
To resume (i.e., continue) a program suspend operation, execute the Program Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume and complete the program operation. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 21, "Program Suspend/Resume Flowchart" on page 62).
Datasheet
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256-Mbit J3 (x8/x16)
12.0
Erase Operations
Flash erasing is performed on a block basis; therefore, only one block can be erased at a time. Once a block is erased, all bits within that block will read as a logic level one. To determine the status of a block erase, poll the Status Register and analyze the bits. This following section describes block erase operations in detail.
12.1
Block Erase
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires an appropriate address within the block to be erased (erase changes all block data to FFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs SRD when read (see Figure 22, "Block Erase Flowchart" on page 63). The CPU can detect block erase completion by analyzing the output of the STS signal or SR.7. Toggle OE#, CE0, CE1, or CE2 to update the Status Register. When the block erase is complete, SR.5 should be checked. If a block erase error is detected, the Status Register should be cleared before system software attempts corrective actions. The CUI remains in Read Status Register mode until a new command is issued. This two-step command sequence of setup followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both SR.4 and SR.5 being set. Also, reliable block erasure can only occur when VCC is valid and VPEN = VPENH. If block erase is attempted while VPEN VPENLK, SR.3 and SR.5 will be set. Successful block erase requires that the corresponding block lock-bit be cleared. If block erase is attempted when the corresponding block lock-bit is set, SR.1 and SR.5 will be set.
12.2
Block Erase Suspend
The Block Erase Suspend command allows block-erase interruption to read or program data in another block of memory. Once the block erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs SRD when read after the Block Erase Suspend command is written. Polling SR.7 then SR.6 can determine when the block erase operation has been suspended (both will be set). In default mode, STS will also transition to VOH. Specification tWHRH defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A program command sequence can also be issued during erase suspend to program data in other blocks. During a program operation with block erase suspended, SR.7 will return to "0" and STS output (in default mode) will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. Using the Program Suspend command, a program operation can also be suspended. Resuming a suspended programming operation by issuing the Program Resume command allows continuing of the suspended programming operation. To resume the suspended erase, the user must wait for the programming operation to complete before issuing the Block Erase Resume command.
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256-Mbit J3 (x8/x16)
The only other valid commands while block erase is suspended are Read Query, Read Status Register, Clear Status Register, Configure, and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. SR.6 and SR.7 will automatically clear and STS (in default mode) will return to VOL. After the Erase Resume command is written, the device automatically outputs SRD when read (see Figure 23, "Block Erase Suspend/Resume Flowchart" on page 64). VPEN must remain at VPENH (the same VPEN level used for block erase) while block erase is suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
12.3
Erase Resume
To resume (i.e., continue) an erase suspend operation, execute the Erase Resume command. The Resume command can be written to any device address. When a program operation is nested within an erase suspend operation and the Program Suspend command is issued, the device will suspend the program operation. When the Resume command is issued, the device will resume the program operations first. Once the nested program operation is completed, an additional Resume command is required to complete the block erase operation. The device supports a maximum suspend/resume of two nested routines. See Figure 22, "Block Erase Flowchart" on page 63.
Datasheet
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256-Mbit J3 (x8/x16)
13.0
Security Modes
This device offers both hardware and software security features. Block lock operations, PRs, and VPEN allow the user to implement various levels of data protection. The following section describes security features in detail. Other security features are available that are not described in this datasheet. Please contact your local Intel Field Representative for more information.
13.1
Set Block Lock-Bit
A flexible block locking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations. Individual block lock-bits can be set using the Set Block Lock-Bit command. This command is invalid while the WSM is running or the device is suspended. Set block lock-bit commands are executed by a two-cycle sequence. The set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). The WSM then controls the set lock-bit algorithm. After the sequence is written, the device automatically outputs Status Register data when read (see Figure 24 on page 65). The CPU can detect the completion of the set lock-bit event by analyzing the STS signal output or SR.7. When the set lock-bit operation is complete, SR.4 should be checked. If an error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until a new command is issued. This two-step sequence of setup followed by execution ensures that lock-bits are not accidentally set. An invalid Set Block Lock-Bit command will result in SR.4 and SR.5 being set. Also, reliable operations occur only when VCC and VPEN are valid. With VPEN VPENLK, lock-bit contents are protected against alteration.
13.2
Clear Block Lock-Bits
All set block lock-bits are cleared in parallel via the Clear Block Lock-Bits command. Block lockbits can be cleared using only the Clear Block Lock-Bits command. This command is invalid while the WSM is running or the device is suspended. Clear block lock-bits command is executed by a two-cycle sequence. A clear block lock-bits setup is first written. The device automatically outputs Status Register data when read (see Figure 25 on page 66). The CPU can detect completion of the clear block lock-bits event by analyzing the STS signal output or SR.7. When the operation is complete, SR.5 should be checked. If a clear block lock-bit error is detected, the Status Register should be cleared. The CUI will remain in Read Status Register mode until another command is issued.
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256-Mbit J3 (x8/x16)
This two-step sequence of setup followed by execution ensures that block lock-bits are not accidentally cleared. An invalid Clear Block Lock-Bits command sequence will result in SR.4 and SR.5 being set. Also, a reliable clear block lock-bits operation can only occur when VCC and VPEN are valid. If a clear block lock-bits operation is attempted while VPEN VPENLK, SR.3 and SR.5 will be set. If a clear block lock-bits operation is aborted due to VPEN or VCC transitioning out of valid range, block lock-bit values are left in an undetermined state. A repeat of clear block lock-bits is required to initialize block lock-bit contents to known values.
13.3
Protection Register Program
The Intel StrataFlash(R) memory (J3) includes a 128-bit Protection Register (PR) that can be used to increase the security of a system design. For example, the number contained in the PR can be used to "mate" the flash component with other system components such as the CPU or ASIC, preventing device substitution. The 128-bits of the PR are divided into two 64-bit segments. One of the segments is programmed at the Intel factory with a unique 64-bit number, which is unalterable. The other segment is left blank for customer designers to program as desired. Once the customer segment is programmed, it can be locked to prevent further programming.
13.3.1
Reading the Protection Register
The Protection Register is read in the identification read mode. The device is switched to this mode by issuing the Read Identifier command (0x90). Once in this mode, read cycles from addresses shown in Table 8 or Table 21 retrieve the specified information. To return to read array mode, write the Read Array command (0xFF).
13.3.2
Programming the Protection Register
Protection Register bits are programmed using the two-cycle Protection Program command. The 64-bit number is programmed 16 bits at a time for word-wide configuration and eight bits at a time for byte-wide configuration. First write the Protection Program Setup command, 0xC0. The next write to the device will latch in address and data and program the specified location. The allowable addresses are shown in Table 8 or Table 21. See Figure 26, "Protection Register Programming Flowchart" on page 67 Any attempt to address Protection Program commands outside the defined PR address space will result in a Status Register error (SR.4 will be set). Attempting to program a locked PR segment will result in a Status Register error (SR.4 and SR.1 will be set).
13.3.3
Locking the Protection Register
The user-programmable segment of the Protection Register is lockable by programming Bit 1 of the PLR to 0. Bit 0 of this location is programmed to 0 at the Intel factory to protect the unique device number. Bit 1 is set using the Protection Program command to program "0xFFFD" to the PLR. After these bits have been programmed, no further changes can be made to the values stored in the Protection Register. Protection Program commands to a locked section will result in a Status Register error (SR.4 and SR.1 will be set). PR lockout state is not reversible.
Datasheet
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256-Mbit J3 (x8/x16)
Figure 17. Protection Register Memory Map
Word Address
0x88
A[24:1]: 256 Mbit A[23:1]: 128 Mbit
A[22:1]: 64 Mbit A[21:1]: 32 Mbit
64-bit Segment (User-Programmable) 0x85 0x84 0x81 Lock Register 0 0x80
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
128-Bit Protection Register 0 64-bit Segment (Factory-Programmed)
NOTE: A0 is not used in x16 mode when accessing the Protection Register map (See Table 8 for x16 addressing). For x8 mode A0 is used (See Table 21 for x8 addressing).
Table 20. Word-Wide Protection Register Addressing
Word LOCK 0 1 2 3 4 5 6 7 Use Both Factory Factory Factory Factory User User User User A8 1 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 1 A3 0 0 0 0 1 1 1 1 0 A2 0 0 1 1 0 0 1 1 0 A1 0 1 0 1 0 1 0 1 0
Table 21. Byte-Wide Protection Register Addressing (Sheet 1 of 2)
Byte LOCK LOCK 0 1 2 3 4 5 Use Both Both Factory Factory Factory Factory Factory Factory A8 1 1 1 1 1 1 1 1 A7 0 0 0 0 0 0 0 0 A6 0 0 0 0 0 0 0 0 A5 0 0 0 0 0 0 0 0 A4 0 0 0 0 0 0 0 0 A3 0 0 0 0 0 0 0 0 A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1
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Datasheet
256-Mbit J3 (x8/x16)
Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)
6 7 8 9 A B C D E F Factory Factory User User User User User User User User 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register, i.e.g., A[MAX:9] = 0.
13.4
Array Protection
The VPEN signal is a hardware mechanism to prohibit array alteration. When the VPEN voltage is below the VPENLK voltage, array contents cannot be altered. To ensure a proper erase or program operation, VPEN must be set to a valid voltage level. To determine the status of an erase or program operation, poll the Status Register and analyze the bits.
Datasheet
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256-Mbit J3 (x8/x16)
14.0
Special Modes
This section describes how to read the status, ID, and CFI registers. This section also details how to configure the STS signal.
14.1
Set Read Configuration Register Command
This command is no longer supported on J3A or J3C. The J3A device will ignore this command, while the J3C device will result in an invalid command sequence (SR.4 and SR.5 =1).
14.2
Status (STS)
The Status (STS) signal can be configured to different states using the Configuration command. Once the STS signal has been configured, it remains in that configuration until another configuration command is issued or RP# is asserted low. Initially, the STS signal defaults to RY/ BY# operation where RY/BY# low indicates that the WSM is busy. RY/BY# high indicates that the state machine is ready for a new operation or suspended. Table 22, "STS Configuration Coding Definitions" on page 50 displays the possible STS configurations. To reconfigure the Status (STS) signal to other modes, the Configuration command is given followed by the desired configuration code. The three alternate configurations are all pulse mode for use as a system interrupt as described below. For these configurations, bit 0 controls Erase Complete interrupt pulse, and bit 1 controls Program Complete interrupt pulse. Supplying the 0x00 configuration code with the Configuration command resets the STS signal to the default RY/BY# level mode. The possible configurations and their usage are described in Table 22, "STS Configuration Coding Definitions" on page 50. The Configuration command may only be given when the device is not busy or suspended. Check SR.7 for device status. An invalid configuration code will result in both SR.4 and SR.5 being set. When configured in one of the pulse modes, the STS signal pulses low with a typical pulse width of 250 ns.
Table 22. STS Configuration Coding Definitions
D7 D6 D5 D4 D3 D2 D1 Pulse on Program Complete (1) Notes
Used to control HOLD to a memory controller to prevent accessing a flash memory subsystem while any flash device's WSM is busy. Used to generate a system interrupt pulse when any flash device in an array has completed a block erase. Helpful for reformatting blocks after file system free space reclamation or "cleanup."
D0 Pulse on Erase Complete (1)
Reserved
D[1:0] = STS Configuration Codes
00 = default, level mode; device ready indication 01 = pulse on Erase Complete
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Datasheet
256-Mbit J3 (x8/x16)
Table 22. STS Configuration Coding Definitions
D7 D6 D5 D4 D3 D2 D1 Pulse on Program Complete (1) Notes
Used to generate a system interrupt pulse when any flash device in an array has completed a program operation. Provides highest performance for servicing continuous buffer write operations. Used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed, when a common interrupt service routine is desired.
D0 Pulse on Erase Complete (1)
Reserved
D[1:0] = STS Configuration Codes
10 = pulse on Program Complete 11 = pulse on Erase or Program Complete
NOTES: 1. When configured in one of the pulse modes, STS pulses low with a typical pulse width of 250 ns. 2. An invalid configuration code will result in both SR.4 and SR.5 being set.
Datasheet
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256-Mbit J3 (x8/x16)
Appendix A Common Flash Interface
The Common Flash Interface (CFI) specification outlines device and host system software interrogation handshake which allows specific vendor-specified software algorithms to be used for entire families of devices. This allows device independent, JEDEC ID-independent, and forwardand backward-compatible software support for the specified flash device families. It allows flash vendors to standardize their existing interfaces for long-term compatibility. This appendix defines the data structure or "database" returned by the Common Flash Interface (CFI) Query command. System software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. Once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. The Query command is part of an overall specification for multiple command set and control interface descriptions called Common Flash Interface, or CFI.
A.1
Query Structure Output
The Query "database" allows system software to gain information for controlling the flash component. This section describes the device's CFI-compliant interface that allows the host system to access Query data. Query data are always presented on the lowest-order data outputs (D[7:0]) only. The numerical offset value is the address relative to the maximum bus width supported by the device. On this family of devices, the Query table device starting address is a 10h, which is a word address for x16 devices. For a word-wide (x16) device, the first two bytes of the Query structure, "Q" and "R" in ASCII, appear on the low byte at word addresses 10h and 11h. This CFI-compliant device outputs 00H data on upper bytes. Thus, the device outputs ASCII "Q" in the low byte (D[7:0]) and 0x00 (00h) in the high byte (D[15:8]). At Query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. In all of the following tables, addresses and data are represented in hexadecimal notation, so the "h" suffix has been dropped. In addition, since the upper byte of word-wide devices is always "00h," the leading "00" has been dropped from the table notation and only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h on the upper byte in this mode.
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256-Mbit J3 (x8/x16)
Table 23. Summary of Query Structure Output as a Function of Device and Mode
Device Type/ Mode Query start location in maximum device bus width addresses Query data with maximum device bus width addressing Hex Offset x16 device x16 mode x16 device x8 mode 10h 10: 11: 12: Hex Code 0051 0052 0059 N/A(1) ASCII Value "Q" "R" "Y" Query data with byte addressing Hex Offset 20: 21: 22: 20: 21: 22: Hex Code 51 00 52 51 51 52 ASCII Value "Q" "Null" "R" "Q" "Q" "R"
N/A(1)
NOTE: 1. The system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. Therefore, word addressing, where these lower addresses are not toggled by the system, is "Not Applicable" for x8-configured devices.
Table 24. Example of Query Structure Output of a x16- and x8-Capable Device
Word Addressing Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h ... 0051 0052 0059 P_IDLO P_IDHI PLO PHI A_IDLO A_IDHI ... Hex Code D15-D0 "Q" "R" "Y" PrVendor ID # PrVendor TblAdr AltVendor ID # ... Value Offset A7-A0 20h 21h 22h 23h 24h 25h 26h 27h 28h ... 51 51 52 52 59 59 P_IDLO P_IDLO P_IDHI ... Byte Addressing Hex Code D7-D0 "Q" "Q" "R" "R" "Y" "Y" PrVendor ID # ID # ... Value
A.2
Query Structure Overview
The Query command causes the flash component to display the Common Flash Interface (CFI) Query structure or "database." The structure sub-sections and address locations are summarized below. See AP-646 Common Flash Interface (CFI) and Command Sets (order number 292204) for a full description of CFI commands. The following sections describe the Query structure sub-sections in detail.
Datasheet
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256-Mbit J3 (x8/x16)
Table 25. Query Structure
Offset 00h 01h (BA+2)h(2) 04-0Fh 10h 1Bh 27h P(3) Block Status Register Reserved CFI Query Identification String System Interface Information Device Geometry Definition Primary Intel-Specific Extended Query Table Sub-Section Name Device Code Block-Specific Information Reserved for Vendor-Specific Information Reserved for Vendor-Specific Information Command Set ID and Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific to the Primary Vendor Algorithm Description Manufacturer Code Notes 1 1 1,2 1 1 1 1 1,3
NOTES: 1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. BA = Block Address beginning location (i.e., 02000h is block 2's beginning location when the block size is 128 Kbyte). 3. Offset 15 defines "P" which points to the Primary Intel-Specific Extended Query Table.
A.3
Block Status Register
The block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations.
Table 26. Block Status Register
Offset (BA+2)h
(1)
Length 1
Description Block Lock Status Register BSR.0 Block Lock Status 0 = Unlocked 1 = Locked BSR 1-7: Reserved for Future Use
Address BA+2: BA+2:
Value --00 or --01 (bit 0): 0 or 1
BA+2: (bit 1-7): 0 NOTE: 1. BA = The beginning location of a Block Address (i.e., 008000h is block 1's (64-KB block) beginning location in word mode).
A.4
CFI Query Identification String
The CFI Query Identification String provides verification that the component supports the Common Flash Interface specification. It also indicates the specification version and supported vendor-specified command set(s).
Table 27. CFI Identification (Sheet 1 of 2)
Offset Length Description Add. 10 11: 12: 13: 14: 15: 16: 17: Hex Code --51 --52 --59 --01 --00 --31 --00 --00 Value "Q" "R" "Y"
10h 13h 15h 17h
3 2 2 2
Query-unique ASCII string "QRY" Primary vendor command set and control interface ID code. 16-bit ID code for vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command set and control interface ID code.
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256-Mbit J3 (x8/x16)
Table 27. CFI Identification (Sheet 2 of 2)
Offset Length Description 0000h means no second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists Add. 18: 19: 1A: Hex Code --00 --00 --00 Value
19h
2
A.5
System Interface Information
The following device information can optimize system interface software.
Table 28. System Interface Information
Offset 1Bh Length 1 Description VCC logic supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VCC logic supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 BCD volts VPP [programming] supply minimum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts VPP [programming] supply maximum program/erase voltage bits 0-3 BCD 100 mV bits 4-7 HEX volts "n" such that typical single word program time-out = 2n s "n" such that typical max. buffer write time-out = 2n s "n" such that typical block erase time-out = 2n ms "n" such that typical full chip erase time-out = 2n ms "n" such that maximum word program time-out = 2n times typical "n" such that maximum buffer write time-out = 2n times typical "n" such that maximum block erase time-out = 2n times typical "n" such that maximum chip erase time-out = 2n times typical Add. 1B: Hex Code --27 Value 2.7 V
1Ch
1
1C:
--36
3.6 V
1Dh
1
1D:
--00
0.0 V
1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h
1 1 1 1 1 1 1 1 1
1E: 1F: 20: 21: 22: 23: 24: 25: 26:
--00 --08 --08 --0A --00 --04 --04 --04 --00
0.0 V 256 s 256 s 1s NA 2 ms 2 ms 16 s NA
A.6
Device Geometry Definition
This field provides critical details of the flash device geometry.
Table 29. Device Geometry Definition (Sheet 1 of 2)
Offset 27h 28h 2Ah Length 1 2 2 Description "n" such that device size = 2n in number of bytes Flash device interface: x8 async x16 async x8/x16 async 28:00,29:00 28:01,29:00 28:02,29:00 "n" such that maximum number of bytes in write buffer = 2n Code See Table Below 27: 28: 29: 2A: 2B: --02 --00 --05 --00 x8/ x16 32
Datasheet
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256-Mbit J3 (x8/x16)
Table 29. Device Geometry Definition (Sheet 2 of 2)
Offset Length Description Number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in "bulk" 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. Symmetrically blocked partitions have one blocking region 4. Partition size = (total blocks) x (individual block size) Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes Code See Table Below
2Ch
1
2C:
--01
1
2Dh
4
2D: 2E: 2F: 30:
Device Geometry Definition
Address 27: 28: 29: 2A: 2B: 2C: 2D: 2E: 2F: 30: 32 Mbit --16 --02 --00 --05 --00 --01 --1F --00 --00 --02 64 Mbit --17 --02 --00 --05 --00 --01 --3F --00 --00 --02 128 Mbit --18 --02 --00 --05 --00 --01 --7F --00 --00 --02 256Mbit --19 --02 -00 -05 -00 -01 -FF --00 --00 --02
A.7
Primary-Vendor Specific Extended Query Table
Certain flash features and commands are optional. The Primary Vendor-Specific Extended Query table specifies this and other similar information.
Table 30. Primary Vendor-Specific Extended Query (Sheet 1 of 2)
Offset(1) P = 31h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h Length 3 Description (Optional Flash Features and Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Add. 31: 32: 33: 34: 35: Hex Code --50 --52 --49 --31 --31 Value "P" "R" "I" "1" "1"
1 1
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Datasheet
256-Mbit J3 (x8/x16)
Table 30. Primary Vendor-Specific Extended Query (Sheet 2 of 2)
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Optional feature and command support (1=yes, 0=no) bits 9-31 are reserved; undefined bits are "0." If bit 31 is "1" then another 31 bit field of optional features follows at the end of the bit-30 field. bit 0 Chip erase supported bit 1 Suspend erase supported bit 2 Suspend program supported bit 3 Legacy lock/unlock supported bit 4 Queued erase supported bit 5 Instant Individual block locking supported bit 6 Protection bits supported bit 7 Page-mode read supported bit 8 Synchronous read supported Supported functions after suspend: read Array, Status, Query Other supported operations are: bits 1-7 reserved; undefined bits are "0" bit 0 Program supported after erase suspend Block status register mask bits 2-15 are Reserved; undefined bits are "0" bit 0 Block Lock-Bit Status register active bit 1 Block Lock-Down Bit Status active VCC logic supply highest performance program/erase voltage bits 0-3 BCD value in 100 mV bits 4-7 BCD value in volts VPP optimum program/erase supply voltage bits 0-3 BCD value in 100 mV bits 4-7 HEX value in volts Add. Hex Code Value
(P+5)h (P+6)h (P+7)h (P+8)h
4
36: --0A 37: --00 38: --00 39: --00 bit 0 = 0 bit 1 = 1 bit 2 = 1 bit 3 = 1(1) bit 4 = 0 bit 5 = 0 bit 6 = 1 bit 7 = 1 bit 8 = 0 3A: --01
No Yes Yes Yes(1) No No Yes Yes No
(P+9)h
1
(P+A)h (P+B)h
2
bit 0 = 1 3B: --01 3C: --00 bit 0 = 1 bit 1 = 0 3D: --33
Yes
Yes No 3.3 V
(P+C)h
1
(P+D)h
1
3E:
--00
0.0 V
NOTE: 1. Future devices may not support the described "Legacy Lock/Unlock" function. Thus bit 3 would have a value of "0."
Datasheet
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256-Mbit J3 (x8/x16)
Table 31. Protection Register Information
Offset(1) P = 31h (P+E)h Length 1 Description (Optional Flash Features and Commands) Number of Protection register fields in JEDEC ID space. "00h," indicates that 256 protection bytes are available Protection Field 1: Protection Description This field describes user-available One Time Programmable (OTP) Protection Register bytes. Some are pre-programmed with device-unique serial numbers. Others are userprogrammable. Bits 0-15 point to the Protection Register lock byte, the section's first byte. The following bytes are factory pre-programmed and user-programmable. bits 0-7 = Lock/bytes JEDEC-plane physical low address bits 8-15 = Lock/bytes JEDEC-plane physical high address bits 16-23 = "n" such that 2n = factory pre-programmed bytes bits 24-31 = "n" such that 2n = user-programmable bytes Add. 3F: Hex Code --01 Value 01
40: 41: 42: 43:
--80 --00 --03 --03
80h 00h 8bytes 8bytes
(P+F)h (P+10)h (P+11)h (P+12)h
4
NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
Table 32. Burst Read Information
Offset(1) P = 31h Length Description (Optional Flash Features and Commands) Page Mode Read capability (P+13)h 1 bits 0-7 = "n" such that 2n HEX value represents the number of read-page bytes. See offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. Number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. Reserved for future use 44: --03 8 byte Add. Hex Code Value
(P+14)h
1
45: 46:
--00
0
(P+15)h NOTE: 1. The variable P is a pointer which is defined at CFI offset 15h.
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Appendix B Flow Charts
Figure 18. Write to Buffer Flowchart
Start
Setup - Write 0xE8 - Block Address
Check Buffer Status - Perform read operation - Read Ready Status on signal SR7
SR7 = 1?
No
Yes Word Count - Address = block address - Data = word count minus 1 (Valid range = 0x00 to0x1F)
Load Buffer - Fill write buffer up to word count - Address = within buffer range - Data = user data
Confirm - Write 0xD0 - Block address
Read Status Register (SR)
No SR7 = 1?
Yes Full Status Register Check (if desired)
End
Datasheet
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256-Mbit J3 (x8/x16)
Figure 19. Status Register Flowchart
Start
Command Cycle - Issue Status Register Command - Address = any dev ice address - Data = 0x70
Data Cycle - Read Status Register SR[7:0]
SR7 = '1'
No
Y es
- Set/Reset by WSM
SR6 = '1'
Y es
Erase Suspend See Suspend/Resume Flowchart
No
SR2 = '1'
Y es
Program Suspend See Suspend/Resume Flowchart
No
SR5 = '1'
Y es
SR4 = '1'
Y es
Error Command Sequence
No
No Error Erase Failure
Y es SR4 = '1'
Error Program Failure
- Set by WSM - Reset by user - See Clear Status Register Command
No
SR3 = '1'
Y es
Error V PEN < VPENLK
No
SR1 = '1'
Y es
Error Block Locked
No
End
0606_07A
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Datasheet
256-Mbit J3 (x8/x16) Figure 20. Byte/Word Program Flowchart
Start
Bus Operation Write Write
Command Setup Byte/ Word Program Byte/Word Program
Comments Data = 40H Addr = Location to Be Programmed Data = Data to Be Programmed Addr = Location to Be Programmed Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 40H, Address Write Data and Address Read Status Register 0 1 Full Status Check if Desired Byte/Word Program Complete
Read (Note 1) Standby
SR.7 =
1. Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR full status check can be done after each program operation, or after a sequence of programming operations. Write FFH after the last program operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 SR.1 = 0 1 SR.4 = 0 Byte/Word Program Successful Programming Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming to Voltage Error Detect Check SR.1 1 = Device Protect Detect RP# = V IH, Block Lock-Bit Is Set Only required for systems implemeting lock-bit configuration. Check SR.4 1 = Programming Error
1 Device Protect Error
Standby
Toggling OE# (low to high to low) updates the status register. This can be done in place of issuing the Read Status Register command. Repeat for subsequent programming operations. SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
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256-Mbit J3 (x8/x16)
Figure 21. Program Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Program Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Programming Suspended 0 = Programming Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.2 = Programming Completed Write 1 Write FFH Read
Read Array
Data = FFH Addr = X Read array locations other than that being programmed.
Program Resume
Data = D0H Addr = X
Read Data Array
No Done Reading Yes Write D0H Write FFH
Programming Resumed
Read Array Data
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256-Mbit J3 (x8/x16)
Figure 22. Block Erase Flowchart
Bus Operation Write Issue Single Block Erase Command 20H, Block Address Write (Note 1)
Start
Command Erase Block Erase Confirm
Comments Data = 20H Addr = Block Address Data = D0H Addr = X Status register data With the device enabled, OE# low updates SR Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy
Read
Standby Write Confirm D0H Block Address
1. The Erase Confirm byte must follow Erase Setup. This device does not support erase queuing. Please see Application note AP-646 For software erase queuing compatibility. Full status check can be done after all erase and write sequences complete. Write FFH after the last operation to reset the device to read array mode. Suspend Erase Loop
Read Status Register No
SR.7 =
0
Suspend Erase
Yes
1 Full Status Check if Desired
Erase Flash Block(s) Complete
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256-Mbit J3 (x8/x16)
Figure 23. Block Erase Suspend/Resume Flowchart
Bus Operation Write Write B0H Read
Start
Command Erase Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 - WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed
Read Status Register
Standby
0 SR.7 =
Standby
Write 1 0 SR.6 = Block Erase Completed
Erase Resume
Data = D0H Addr = X
1 Read Read or Program? Read Array Data Done? Yes Write D0H Write FFH Program Loop Program
No
Block Erase Resumed
Read Array Data
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256-Mbit J3 (x8/x16)
Figure 24. Set Block Lock-Bit Flowchart
Start
Bus Operation Write
Command Set Block Lock-Bit Setup Set Block Lock-Bit Confirm
Comments Data = 60H Addr =Block Address Data = 01H Addr = Block Address Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H, Block Address Write 01H, Block Address
Write
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired
0
Repeat for subsequent lock-bit operations. Full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. Write FFH after the last lock-bit set operation to place device in read array mode.
Set Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.4 = 0 Set Lock-Bit Successful Set Lock-Bit Error Command Sequence Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.4 1 = Set Lock-Bit Error
Standby
SR.5, SR.4 and SR.3 are only cleared by the Clear Status Register command, in cases where multiple lock-bits are set before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
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256-Mbit J3 (x8/x16)
Figure 25. Clear Lock-Bit Flowchart
Start
Bus Operation Write
Command Clear Block Lock-Bits Setup Clear Block or Lock-Bits Confirm
Comments Data = 60H Addr = X Data = D0H Addr = X Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write 60H
Write
Write D0H
Read
Read Status Register
Standby
SR.7 = 1 Full Status Check if Desired Clear Block Lock-Bits Complete
0
Write FFH after the clear lock-bits operation to place device in read array mode.
FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1 SR.3 = 0 1 SR.4,5 = 0 1 SR.5 = 0 Clear Block Lock-Bits Successful Clear Block Lock-Bits Error Command Sequence Error Voltage Range Error
Standby Bus Operation Standby Command Comments Check SR.3 1 = Programming Voltage Error Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Clear Block Lock-Bits Error
Standby
SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register command. If an error is detected, clear the status register before attempting retry or other error recovery.
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Figure 26. Protection Register Programming Flowchart
Start
Bus Operation Write Write
Command Protection Program Setup Protection Program
Comments Data = C0H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Write C0H (Protection Reg. Program Setup) Write Protect. Register Address/Data
Read
Standby
Read Status Register
SR.7 = 1? Yes Full Status Check if Desired
No
Protection Program operations can only be addressed within the protection register address space. Addresses outside the defined space will return an error. Repeat for subsequent programming operations. SR Full Status Check can be done after each program or after a sequence of program operations. Write FFH after the last program operation to reset device to read array mode.
Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) 1, 1 SR.3, SR.4 = VPEN Range Error 0,1 SR.1, SR.4 =
Standby Bus Operation Standby Command Comments SR.1 SR.3 SR.4 0 1 1 V PEN Low 0 0 1 Prot. Reg. Prog. Error Register Locked: Aborted
1
0
1
Protection Register Programming Error Attempted Program to Locked Register Aborted
Standby
SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine.
1,1 SR.1, SR.4 =
SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases of multiple protection register program operations before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery.
Program Successful
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256-Mbit J3 (x8/x16)
Appendix C Design Considerations
C.1 Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1, CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see Table 13) while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while de-selected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
C.2
STS and Block Erase, Program, and Lock-Bit Configuration Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. It is recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to High Z when the WSM has finished executing the internal algorithm. For alternate configurations of the STS signal, see the Configuration command. STS can be connected to an interrupt input of the system CPU or controller. It is active at all times. STS, in default mode, is also High Z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode.
C.3
Input Signal Transitions--Reducing Overshoots and Undershoots When Using Buffers or Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications. (See "DC Voltage Characteristics" on page 20.) Many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. Internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. These internal output-damping resistors help reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or lightdrive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For additional information, please refer to AP-647, 5 Volt Intel StrataFlash(R) Memory Design Guide (Order Number: 292205).
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C.4
VCC, VPEN, RP# Transitions
Block erase, program, and lock-bit configuration are not guaranteed if VPEN or VCC falls outside of the specified operating ranges, or RP# VIH. If RP# transitions to VIL during block erase, program, or lock-bit configuration, STS (in default mode) will remain low for a maximum time of tPLPH + tPHRH until the reset operation is complete. Then, the operation will abort and the device will enter reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. Therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. Device power-off or RP# = VIL clears the Status Register. The CUI latches commands issued by system software and is not altered by VPEN, CE0, CE1, or CE2 transitions, or WSM actions. Its state is read array mode upon power-up, after exit from reset/ power-down mode, or after VCC transitions below VLKO. VCC must be kept at or above VPEN during VCC transitions. After block erase, program, or lock-bit configuration, even after VPEN transitions down to VPENLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired. VPEN must be kept at or below VCC during VPEN transitions.
C.5
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed.
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256-Mbit J3 (x8/x16)
Appendix D Additional Information
Order Number
(R)
Document/Tool Intel StrataFlashTM Memory (J3); 28F256J3, 28F128J3, 28F640J3, 28F320J3 Specification Update Intel(R) Persistent Storage Manager (IPSM) User's Guide Software Manual Intel(R) Flash Data Integrator (FDI) User's Guide Software Manual Intel StrataFlash(R) Synchronous Memory (K3/K18); 28F640K3, 28F640K18, 28F128K3, 28F128K18, 28F256K3, 28F256K18 AP-732 3 Volt Intel StrataFlash(R) Memory J3 to K3/K18 Migration Guide AP-689 Using Intel(R) Persistent Storage Manager 5 Volt Intel(R) StrataFlashTM MemoryI28F320J5 and 28F640J5 datasheet AP-677 Intel(R) StrataFlashTM Memory Technology AP-664 Designing Intel(R) StrataFlashTM Memory into Intel(R) Architecture AP-663 Using the Intel(R) StrataFlashTM Memory Write Buffer AP-660 Migration Guide to 3 Volt Intel(R) StrataFlashTM Memory AP-646 Common Flash Interface (CFI) and Command Sets Intel(R) Wireless Communications and Computing Package User's Guide
298130 298136 297833 290737 292280 292237 290606 297859 292222 292221 292218 292204 253418
1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. For the most current information on Intel StrataFlash memory, visit our website at http:// developer.intel.com/design/flash/isf.
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Appendix E Ordering Information
PC2 8 F 2 5 6 J 3 C- 1 2 5
Package E = 56-Lead TSOP (J3A, 802) TE= 56-Lead TSOP (J3C, 803) JS = Pb-Free 56-TSOP RC = 64-Ball Easy BGA GE = 48-Ball VFBGA PC = 64-Ball Pb-Free Easy BGA
1 Access Speed (ns) 256 Mbit = 125 128 Mbit = 150, 120 64 Mbit = 120, 115 32 Mbit = 110
A = Intel(R) 0.25 micron lithography C = Intel(R) 0.18 micron lithography Voltage (V /V PEN) CC 3 = 3 V/3 V Product Family J = Intel StrataFlash (R) memory, 2 bits-per-cell
Product line designator for all Intel (R) Flash products
Device Density 256 = x8/x16 (256 Mbit) 128 = x8/x16 (128 Mbit) 640 = x8/x16 (64 Mbit) 320 = x8/x16 (32 Mbit)
NOTE: 1. Speeds are for either the standard asynchronous read access times or for the first access of a page-mode read sequence.
VALID COMBINATIONS
56-Lead TSOP E28F320J3A-110 E28F640J3A-120 E28F128J3A-150 TE28F320J3C-110 TE28F640J3C-115 TE28F640J3C-120 TE28F128J3C-120 TE28F128J3C-150 TE28F256J3C-125 56-Lead Pb-Free TSOP JS28F256J3C125 JS28F128J3C120 JS28F640J3C115 JS28F320J3C110 64-Ball Easy BGA RC28F320J3A-110 RC28F640J3A-120 RC28F128J3A-150 RC28F320J3C-110 RC28F640J3C-115 RC28F640J3C-120 RC28F128J3C-120 RC28F128J3C-150 RC28F256J3C-125 64-Ball Pb-Free Easy BGA PC28F256J3C125 PC28F128J3C120 PC28F640J3C115 PC28F320J3C110 48-Ball VF BGA GE28F320J3A-110 GE28F320J3C-110 GE28F640J3C-115 GE28F640J3C-120
Datasheet
71

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